commit	d6e05317f89409453123986540a98541c5e2c048	[log] [tgz]
author	jaquerinte <ivanrodriguezferrandez@gmail.com>	Mon Jun 14 18:16:39 2021 +0200
committer	jaquerinte <ivanrodriguezferrandez@gmail.com>	Mon Jun 14 18:16:39 2021 +0200
tree	371e0ebeb6bff223537213ccfb6e001a9bdec346
parent	062f5978e18f233baaa25d04f917b1d025659108 [diff]

stable version of the code ready for testing

def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[Deleted - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[Deleted - diff]
mag/user_proj_example.mag[Deleted - diff]
mag/user_project_wrapper.mag[Deleted - diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[Deleted - diff]
openlane/user_proj_example/config.tcl[diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
run_test.sh[diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[Deleted - diff]
verilog/dv/Makefile[diff]
verilog/dv/la_test1/la_test1.c[diff]
verilog/dv/la_test10/la_test10.c[diff]
verilog/dv/la_test11/la_test11.c[diff]
verilog/dv/la_test2/la_test2.c[diff]
verilog/dv/la_test3/la_test3.c[diff]
verilog/dv/la_test4/la_test4.c[diff]
verilog/dv/la_test5/la_test5.c[diff]
verilog/dv/la_test6/la_test6.c[diff]
verilog/dv/la_test7/la_test7.c[diff]
verilog/dv/la_test8/la_test8.c[diff]
verilog/dv/la_test9/la_test9.c[diff]
verilog/dv/wb_test1/wb_test1.c[diff]
verilog/dv/wb_test2/wb_test2.c[diff]
verilog/dv/wb_test2/wb_test2.gtkw[diff]
verilog/dv/wb_test3/wb_test3.c[diff]
verilog/dv/wb_test3/wb_test3.gtkw[diff]
verilog/dv/wb_test4/Makefile[Added - diff]
verilog/dv/wb_test4/wb_test4.c[Added - diff]
verilog/dv/wb_test4/wb_test4.gtkw[Added - diff]
verilog/dv/wb_test4/wb_test4_tb.v[Added - diff]
verilog/dv/wb_test5/Makefile[Added - diff]
verilog/dv/wb_test5/wb_test5.c[Added - diff]
verilog/dv/wb_test5/wb_test5.gtkw[Added - diff]
verilog/dv/wb_test5/wb_test5_tb.v[Added - diff]
verilog/dv/wb_test6/Makefile[Added - diff]
verilog/dv/wb_test6/wb_test6.c[Added - diff]
verilog/dv/wb_test6/wb_test6.gtkw[Added - diff]
verilog/dv/wb_test6/wb_test6_tb.v[Added - diff]
verilog/dv/wb_test7/Makefile[Added - diff]
verilog/dv/wb_test7/wb_test7.c[Added - diff]
verilog/dv/wb_test7/wb_test7.gtkw[Added - diff]
verilog/dv/wb_test7/wb_test7_tb.v[Added - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/rtl/ecc_registers/register_data.v[diff]
verilog/rtl/ecc_registers/register_file.v[diff]
verilog/rtl/ecc_registers/state_counters.v[diff]
verilog/rtl/user_proj.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

57 files changed

tree: 371e0ebeb6bff223537213ccfb6e001a9bdec346

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.