change internal structure of the project to add whisbone support to of the internal data sturctures
diff --git a/.gitignore b/.gitignore
index d0abdb0..8752af1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,4 @@
checks/
-*.vcd
\ No newline at end of file
+*.vcd
+*.hex
+*.vvp
\ No newline at end of file
diff --git a/caravel b/caravel
index 576242b..13f2590 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 576242b3e7ffdf58c9d3154ad7cbb39cb73b7aeb
+Subproject commit 13f2590e4b3a74b910dac56a6b757f5a66fd5212
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
index 0f0b284..09df031 100644
--- a/verilog/dv/la_test1/la_test1.c
+++ b/verilog/dv/la_test1/la_test1.c
@@ -52,22 +52,22 @@
// logic analyzer probes.
// I/O 6 is configured for the UART Tx line
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
@@ -127,28 +127,13 @@
reg_la2_data = 0x00000001;
reg_la2_data = 0x00000000;
- if (reg_la3_data == 0x00000020) {
- print("Correct\n");
- }
- else {
- print("Error\n");
- }
-
reg_la0_data = 0x00000005;
reg_la1_data = 0x00000000;
-
-
reg_la2_data = 0x00000001;
reg_la2_data = 0x00000000;
- if (reg_la3_data == 0x00000010) {
- print("Correct\n");
- }
- else {
- print("Error\n");
- }
reg_mprj_datal = 0xAB410000;
print("\n");
diff --git a/verilog/dv/la_test1/la_test1.gtkw b/verilog/dv/la_test1/la_test1.gtkw
new file mode 100644
index 0000000..9f9b4e3
--- /dev/null
+++ b/verilog/dv/la_test1/la_test1.gtkw
@@ -0,0 +1,201 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Thu May 20 07:21:04 2021
+[*]
+[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test1/la_test1.vcd"
+[dumpfile_mtime] "Thu May 20 07:12:28 2021"
+[dumpfile_size] 2289251237
+[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test1/la_test1.gtkw"
+[timestart] 1091000000
+[size] 1848 1016
+[pos] -1 -1
+*-27.000000 1444962500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] la_test1_tb.
+[treeopen] la_test1_tb.uut.
+[treeopen] la_test1_tb.uut.mprj.
+[treeopen] la_test1_tb.uut.mprj.mprj.
+[treeopen] la_test1_tb.uut.mprj.mprj.register_file.
+[treeopen] la_test1_tb.uut.mprj.mprj.register_file.inst_RD.
+[sst_width] 279
+[signals_width] 222
+[sst_expanded] 1
+[sst_vpaned_height] 289
+@200
+-TOP MODULE
+@28
+[color] 5
+la_test1_tb.uut.mprj.mprj.register_file.clk_i
+la_test1_tb.uut.mprj.mprj.register_file.rst_i
+@24
+[color] 4
+la_test1_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
+[color] 2
+la_test1_tb.uut.mprj.mprj.register_file.register_i[2:0]
+@28
+[color] 3
+la_test1_tb.uut.mprj.mprj.register_file.wregister_i
+[color] 3
+la_test1_tb.uut.mprj.mprj.register_file.rregister_i
+@24
+[color] 1
+la_test1_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
+@28
+[color] 2
+la_test1_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@200
+-
+-DATA REGISTER
+@24
+[color] 2
+la_test1_tb.uut.mprj.mprj.register_file.inst_RD.register_i[2:0]
+@22
+[color] 1
+la_test1_tb.uut.mprj.mprj.register_file.inst_RD.data_to_register_i[38:0]
+[color] 7
+la_test1_tb.uut.mprj.mprj.register_file.inst_RD.store_data_o[38:0]
+@200
+-
+-DATA VERIFICATOR
+@c00028
+[color] 1
+la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+@28
+[color] 1
+(0)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(1)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(2)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(3)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(4)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(5)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(6)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(7)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(8)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(9)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(10)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(11)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(12)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(13)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(14)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(15)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(16)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(17)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(18)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(19)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(20)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(21)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(22)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(23)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(24)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(25)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(26)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(27)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(28)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(29)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(30)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(31)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(32)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(33)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(34)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(35)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(36)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(37)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+[color] 1
+(38)la_test1_tb.uut.mprj.mprj.register_file.inst_DV.internal_data_i[38:0]
+@1401200
+-group_end
+@28
+[color] 3
+la_test1_tb.uut.mprj.mprj.register_file.inst_DV.operate_i
+[color] 3
+la_test1_tb.uut.mprj.mprj.register_file.inst_DV.valid_output_o
+[color] 2
+la_test1_tb.uut.mprj.mprj.register_file.inst_DV.operation_result_o[1:0]
+@24
+la_test1_tb.uut.mprj.mprj.register_file.inst_DV.store_data_o[31:0]
+@200
+-
+-IO DATA
+@800022
+la_test1_tb.mprj_io[37:0]
+@28
+(0)la_test1_tb.mprj_io[37:0]
+(1)la_test1_tb.mprj_io[37:0]
+(2)la_test1_tb.mprj_io[37:0]
+(3)la_test1_tb.mprj_io[37:0]
+(4)la_test1_tb.mprj_io[37:0]
+(5)la_test1_tb.mprj_io[37:0]
+(6)la_test1_tb.mprj_io[37:0]
+(7)la_test1_tb.mprj_io[37:0]
+(8)la_test1_tb.mprj_io[37:0]
+(9)la_test1_tb.mprj_io[37:0]
+(10)la_test1_tb.mprj_io[37:0]
+(11)la_test1_tb.mprj_io[37:0]
+(12)la_test1_tb.mprj_io[37:0]
+(13)la_test1_tb.mprj_io[37:0]
+(14)la_test1_tb.mprj_io[37:0]
+(15)la_test1_tb.mprj_io[37:0]
+@29
+(16)la_test1_tb.mprj_io[37:0]
+@28
+(17)la_test1_tb.mprj_io[37:0]
+(18)la_test1_tb.mprj_io[37:0]
+(19)la_test1_tb.mprj_io[37:0]
+(20)la_test1_tb.mprj_io[37:0]
+(21)la_test1_tb.mprj_io[37:0]
+(22)la_test1_tb.mprj_io[37:0]
+(23)la_test1_tb.mprj_io[37:0]
+(24)la_test1_tb.mprj_io[37:0]
+(25)la_test1_tb.mprj_io[37:0]
+(26)la_test1_tb.mprj_io[37:0]
+(27)la_test1_tb.mprj_io[37:0]
+(28)la_test1_tb.mprj_io[37:0]
+(29)la_test1_tb.mprj_io[37:0]
+(30)la_test1_tb.mprj_io[37:0]
+(31)la_test1_tb.mprj_io[37:0]
+(32)la_test1_tb.mprj_io[37:0]
+(33)la_test1_tb.mprj_io[37:0]
+(34)la_test1_tb.mprj_io[37:0]
+(35)la_test1_tb.mprj_io[37:0]
+(36)la_test1_tb.mprj_io[37:0]
+(37)la_test1_tb.mprj_io[37:0]
+@1001200
+-group_end
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/verilog/dv/la_test1/la_test1.hex b/verilog/dv/la_test1/la_test1.hex
index 459e9b8..44b55e0 100755
--- a/verilog/dv/la_test1/la_test1.hex
+++ b/verilog/dv/la_test1/la_test1.hex
@@ -6,7 +6,7 @@
13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
-13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 53
+13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 4D
93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 40 00
63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22
@@ -28,22 +28,22 @@
C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61
82 80 41 11 06 C6 22 C4 00 08 B7 07 00 24 29 67
09 07 98 C3 B7 07 00 26 93 87 07 0A 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 C7 09 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 87 09 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 47 09 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 07 09 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 C7 08 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 87 08 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 47 08 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 07 08 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 C7 07 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 87 07 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 47 07 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 07 07 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 C7 06 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 87 06 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 47 06 09 67 13 07
-97 80 98 C3 B7 07 00 26 93 87 07 06 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 C7 09 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 87 09 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 47 09 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 07 09 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 C7 08 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 87 08 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 47 08 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 07 08 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 C7 07 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 87 07 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 47 07 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 07 07 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 C7 06 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 87 06 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 47 06 09 67 13 07
+87 80 98 C3 B7 07 00 26 93 87 07 06 09 67 13 07
87 80 98 C3 B7 07 00 26 93 87 C7 05 09 67 13 07
87 80 98 C3 B7 07 00 26 93 87 87 05 09 67 13 07
87 80 98 C3 B7 07 00 26 93 87 47 05 09 67 13 07
@@ -76,17 +76,11 @@
B7 07 00 25 A1 07 23 A0 07 00 B7 07 00 25 25 47
98 C3 B7 07 00 25 91 07 23 A0 07 00 B7 07 00 25
A1 07 05 47 98 C3 B7 07 00 25 A1 07 23 A0 07 00
-B7 07 00 25 B1 07 98 43 93 07 00 02 63 18 F7 00
-B7 07 00 10 13 85 87 57 51 39 31 A0 B7 07 00 10
-13 85 47 58 61 31 B7 07 00 25 15 47 98 C3 B7 07
-00 25 91 07 23 A0 07 00 B7 07 00 25 A1 07 05 47
-98 C3 B7 07 00 25 A1 07 23 A0 07 00 B7 07 00 25
-B1 07 98 43 C1 47 63 18 F7 00 B7 07 00 10 13 85
-87 57 A9 31 31 A0 B7 07 00 10 13 85 47 58 3D 39
-B7 07 00 26 B1 07 37 07 41 AB 98 C3 B7 07 00 10
-13 85 C7 58 25 31 B7 07 00 10 13 85 07 59 39 39
-B7 07 00 26 B1 07 37 07 51 AB 98 C3 01 00 B2 40
-22 44 41 01 82 80 00 00 43 6F 72 72 65 63 74 0A
-00 00 00 00 45 72 72 6F 72 0A 00 00 0A 00 00 00
+B7 07 00 25 15 47 98 C3 B7 07 00 25 91 07 23 A0
+07 00 B7 07 00 25 A1 07 05 47 98 C3 B7 07 00 25
+A1 07 23 A0 07 00 B7 07 00 26 B1 07 37 07 41 AB
+98 C3 B7 07 00 10 13 85 C7 52 8D 39 B7 07 00 10
+13 85 07 53 A5 31 B7 07 00 26 B1 07 37 07 51 AB
+98 C3 01 00 B2 40 22 44 41 01 82 80 0A 00 00 00
4D 6F 6E 69 74 6F 72 3A 20 54 65 73 74 20 31 20
50 61 73 73 65 64 0A 0A 00 00 00 00
diff --git a/verilog/dv/la_test1/la_test1.vvp b/verilog/dv/la_test1/la_test1.vvp
deleted file mode 100755
index 86d259f..0000000
--- a/verilog/dv/la_test1/la_test1.vvp
+++ /dev/null
Binary files differ
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index eabf8b4..ca80a15 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -29,7 +29,7 @@
reg power1, power2;
- wire gpio;
+ wire gpio;
wire uart_tx;
wire [37:0] mprj_io;
wire [15:0] checkbits;
@@ -69,6 +69,7 @@
$display("LA Test 1 started");
wait(mprj_io[24:20] == 5'b00010);
wait(mprj_io[24:20] == 5'b00001);
+ $display("LA Test 1 Finish correctly");
//wait(checkbits == 16'h0002);
#10000;
$finish;
diff --git a/verilog/dv/la_test1/test_data.gtkw b/verilog/dv/la_test1/test_data.gtkw
deleted file mode 100644
index 22d7c54..0000000
--- a/verilog/dv/la_test1/test_data.gtkw
+++ /dev/null
@@ -1,34 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
-[*] Wed May 12 10:08:11 2021
-[*]
-[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test1/la_test1.vcd"
-[dumpfile_mtime] "Wed May 12 09:45:31 2021"
-[dumpfile_size] 2291121094
-[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test1/test_data.gtkw"
-[timestart] 310100
-[size] 1848 1016
-[pos] -51 -51
-*-15.000000 412500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[treeopen] la_test1_tb.
-[treeopen] la_test1_tb.uut.
-[treeopen] la_test1_tb.uut.mprj.
-[treeopen] la_test1_tb.uut.mprj.mprj.
-[treeopen] la_test1_tb.uut.mprj.mprj.register_file.
-[treeopen] la_test1_tb.uut.por.porb_level.
-[treeopen] la_test1_tb.uut.rstb_level.lvlshiftdown.
-[treeopen] la_test1_tb.uut.user_id_value.
-[sst_width] 335
-[signals_width] 222
-[sst_expanded] 1
-[sst_vpaned_height] 289
-@28
-la_test1_tb.uut.mprj.mprj.register_file.clk_i
-@22
-la_test1_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
-@28
-la_test1_tb.uut.mprj.mprj.register_file.rregister_i
-@29
-la_test1_tb.uut.mprj.mprj.register_file.wregister_i
-[pattern_trace] 1
-[pattern_trace] 0
diff --git a/verilog/dv/verify.log b/verilog/dv/verify.log
deleted file mode 100644
index e69de29..0000000
--- a/verilog/dv/verify.log
+++ /dev/null
diff --git a/verilog/rtl/ecc_registers/data_verificator.v b/verilog/rtl/ecc_registers/data_verificator.v
index 0272452..711ddd5 100755
--- a/verilog/rtl/ecc_registers/data_verificator.v
+++ b/verilog/rtl/ecc_registers/data_verificator.v
@@ -9,13 +9,13 @@
//***Module***
module data_verificator #(
parameter integer WORD_SIZE = 32,
- parameter integer ECCBITS = 7
+ parameter integer ECCBITS = 7,
+ parameter integer VERIFICATION_PINS = 2
)
(
- input [WORD_SIZE - 1 : 0] internal_data_i ,
- input [ECCBITS - 1 : 0] parity_bits_i ,
+ input [WORD_SIZE + ECCBITS- 1 : 0] internal_data_i ,
input operate_i ,
- output reg [1 : 0] operation_result_o ,
+ output reg [VERIFICATION_PINS - 1 : 0] operation_result_o ,
output reg [WORD_SIZE - 1 : 0] store_data_o ,
output reg valid_output_o
);
@@ -27,30 +27,87 @@
reg valid_output;
reg [WORD_SIZE-1:0] data_store;
reg [WORD_SIZE + ECCBITS -1:0] correction_stage;
- wire [WORD_SIZE + ECCBITS -1:0] data_representation;
+ wire [WORD_SIZE + ECCBITS :0] data_representation;
wire [ECCBITS -1:0] parity_bits;
- assign parity_bits[0] = operate_i ? parity_bits_i[0] ^ internal_data_i[0] ^ internal_data_i[1]^ internal_data_i[3] ^ internal_data_i[4] ^ internal_data_i[6] ^ internal_data_i[8]^ internal_data_i[10] ^ internal_data_i[11] ^ internal_data_i[13]^ internal_data_i[15]^ internal_data_i[17] ^ internal_data_i[19] ^ internal_data_i[21] ^ internal_data_i[23] ^ internal_data_i[25] ^ internal_data_i[26] ^ internal_data_i[28] ^ internal_data_i[30] : 1'b0;
- assign parity_bits[1] = operate_i ? parity_bits_i[1] ^ internal_data_i[0] ^ internal_data_i[2]^ internal_data_i[3] ^ internal_data_i[5] ^ internal_data_i[6] ^ internal_data_i[9]^ internal_data_i[10] ^ internal_data_i[12] ^ internal_data_i[13]^ internal_data_i[16]^ internal_data_i[17] ^ internal_data_i[20] ^ internal_data_i[21] ^ internal_data_i[24] ^ internal_data_i[25] ^ internal_data_i[27] ^ internal_data_i[28] ^ internal_data_i[31] : 1'b0;
- assign parity_bits[2] = operate_i ? parity_bits_i[2] ^ internal_data_i[1] ^ internal_data_i[2]^ internal_data_i[3] ^ internal_data_i[7] ^ internal_data_i[8] ^ internal_data_i[9]^ internal_data_i[10] ^ internal_data_i[14] ^ internal_data_i[15]^ internal_data_i[16]^ internal_data_i[17] ^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] ^ internal_data_i[29] ^ internal_data_i[30] ^ internal_data_i[31] : 1'b0;
- assign parity_bits[3] = operate_i ? parity_bits_i[3] ^ internal_data_i[4] ^ internal_data_i[5]^ internal_data_i[6] ^ internal_data_i[7] ^ internal_data_i[8] ^ internal_data_i[9]^ internal_data_i[10] ^ internal_data_i[18] ^ internal_data_i[19]^ internal_data_i[20]^ internal_data_i[21] ^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] : 1'b0;
- assign parity_bits[4] = operate_i ? parity_bits_i[4] ^ internal_data_i[11] ^ internal_data_i[12] ^ internal_data_i[13]^ internal_data_i[14] ^ internal_data_i[15] ^ internal_data_i[16] ^ internal_data_i[17]^ internal_data_i[18] ^ internal_data_i[19] ^ internal_data_i[20]^ internal_data_i[21]^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] : 1'b0;
- assign parity_bits[5] = operate_i ? parity_bits_i[5] ^ internal_data_i[26] ^ internal_data_i[27]^ internal_data_i[28] ^ internal_data_i[29] ^ internal_data_i[30] ^ internal_data_i[31] : 1'b0;
- assign parity_bits[6] = operate_i ? parity_bits_i[0] ^ parity_bits_i[1] ^ parity_bits_i[2] ^ parity_bits_i[3] ^ parity_bits_i[4] ^ parity_bits_i[5] ^ parity_bits_i[6] ^internal_data_i[0] ^internal_data_i[1] ^ internal_data_i[2] ^ internal_data_i[3] ^ internal_data_i[4]^ internal_data_i[5]^ internal_data_i[6]^ internal_data_i[7]^ internal_data_i[8]^ internal_data_i[9]^ internal_data_i[10]^ internal_data_i[11]^ internal_data_i[12]^ internal_data_i[13]^ internal_data_i[14]^ internal_data_i[15]^ internal_data_i[16]^ internal_data_i[17]^ internal_data_i[18]^ internal_data_i[19]^ internal_data_i[20]^ internal_data_i[21]^ internal_data_i[22]^ internal_data_i[23]^ internal_data_i[24]^ internal_data_i[25]^ internal_data_i[26]^ internal_data_i[27]^ internal_data_i[28]^ internal_data_i[29]^ internal_data_i[30]^ internal_data_i[31] : 1'b0;
+
+ /*
+ #######################################################################################
+ # Conversion table
+ #######################################################################################
+ Position -> value
+ 0: parity_bits_i[0]
+ 1: parity_bits_i[1]
+ 2: internal_data_i[0]
+ 3: parity_bits_i[2]
+ 4: internal_data_i[1]
+ 5: internal_data_i[2]
+ 6: internal_data_i[3]
+ 7: parity_bits_i[3]
+ 8: internal_data_i[4]
+ 9: internal_data_i[5]
+ 10: internal_data_i[6]
+ 11: internal_data_i[7]
+ 12: internal_data_i[8]
+ 13: internal_data_i[9]
+ 14: internal_data_i[10]
+ 15: parity_bits_i[4]
+ 16: internal_data_i[11]
+ 17: internal_data_i[12]
+ 18: internal_data_i[13]
+ 19: internal_data_i[14]
+ 20: internal_data_i[15]
+ 21: internal_data_i[16]
+ 22: internal_data_i[17]
+ 23: internal_data_i[18]
+ 24: internal_data_i[19]
+ 25: internal_data_i[20]
+ 26: internal_data_i[21]
+ 27: internal_data_i[22]
+ 28: internal_data_i[23]
+ 29: internal_data_i[24]
+ 30: internal_data_i[25]
+ 31: parity_bits_i[5]
+ 32: internal_data_i[26]
+ 33: internal_data_i[27]
+ 34: internal_data_i[28]
+ 35: internal_data_i[29]
+ 36: internal_data_i[30]
+ 37: internal_data_i[31]
+ 38: parity_bits_i[6]
+ #######################################################################################
+ */
- assign data_representation = {internal_data_i[31],internal_data_i[30],internal_data_i[29],internal_data_i[28],internal_data_i[27],internal_data_i[26],parity_bits_i[5],internal_data_i[25],internal_data_i[24],internal_data_i[23],internal_data_i[22],internal_data_i[21],internal_data_i[20],internal_data_i[19],internal_data_i[18],internal_data_i[17],internal_data_i[16],internal_data_i[15],internal_data_i[14],internal_data_i[13],internal_data_i[12],internal_data_i[11],parity_bits_i[4],internal_data_i[10],internal_data_i[9],internal_data_i[8],internal_data_i[7],internal_data_i[6],internal_data_i[5],internal_data_i[4],parity_bits_i[3],internal_data_i[3],internal_data_i[2],internal_data_i[1],parity_bits_i[2],internal_data_i[0], parity_bits_i[1], parity_bits_i[0],1'b0};
+
+ assign parity_bits[0] = operate_i ? internal_data_i[0] ^ internal_data_i[2] ^ internal_data_i[4] ^ internal_data_i[6] ^ internal_data_i[8] ^ internal_data_i[10] ^ internal_data_i[12] ^ internal_data_i[14] ^ internal_data_i[16] ^ internal_data_i[18] ^ internal_data_i[20] ^ internal_data_i[22] ^ internal_data_i[24] ^ internal_data_i[26] ^ internal_data_i[28] ^ internal_data_i[30] ^ internal_data_i[32] ^ internal_data_i[34] ^ internal_data_i[36] : 1'b0;
+ //assign parity_bits[0] = operate_i ? parity_bits_i[0] ^ internal_data_i[0] ^ internal_data_i[1]^ internal_data_i[3] ^ internal_data_i[4] ^ internal_data_i[6] ^ internal_data_i[8]^ internal_data_i[10] ^ internal_data_i[11] ^ internal_data_i[13]^ internal_data_i[15]^ internal_data_i[17] ^ internal_data_i[19] ^ internal_data_i[21] ^ internal_data_i[23] ^ internal_data_i[25] ^ internal_data_i[26] ^ internal_data_i[28] ^ internal_data_i[30] : 1'b0;
+ assign parity_bits[1] = operate_i ? internal_data_i[1] ^ internal_data_i[2] ^ internal_data_i[5] ^ internal_data_i[6] ^ internal_data_i[9] ^ internal_data_i[10] ^ internal_data_i[13] ^ internal_data_i[14] ^ internal_data_i[17] ^ internal_data_i[18] ^ internal_data_i[21] ^ internal_data_i[22] ^ internal_data_i[25] ^ internal_data_i[26] ^ internal_data_i[29] ^ internal_data_i[30] ^ internal_data_i[33] ^ internal_data_i[34]^ internal_data_i[37] : 1'b0;
+ //assign parity_bits[1] = operate_i ? parity_bits_i[1] ^ internal_data_i[0] ^ internal_data_i[2]^ internal_data_i[3] ^ internal_data_i[5] ^ internal_data_i[6] ^ internal_data_i[9]^ internal_data_i[10] ^ internal_data_i[12] ^ internal_data_i[13]^ internal_data_i[16]^ internal_data_i[17] ^ internal_data_i[20] ^ internal_data_i[21] ^ internal_data_i[24] ^ internal_data_i[25] ^ internal_data_i[27] ^ internal_data_i[28] ^ internal_data_i[31] : 1'b0;
+ assign parity_bits[2] = operate_i ? internal_data_i[3] ^ internal_data_i[4] ^ internal_data_i[5] ^ internal_data_i[6] ^ internal_data_i[11] ^ internal_data_i[12] ^ internal_data_i[13] ^ internal_data_i[14] ^ internal_data_i[19] ^ internal_data_i[20] ^ internal_data_i[21] ^ internal_data_i[22] ^ internal_data_i[27] ^ internal_data_i[28] ^ internal_data_i[29] ^ internal_data_i[30] ^ internal_data_i[35] ^ internal_data_i[36] ^ internal_data_i[37] : 1'b0;
+ //assign parity_bits[2] = operate_i ? parity_bits_i[2] ^ internal_data_i[1] ^ internal_data_i[2]^ internal_data_i[3] ^ internal_data_i[7] ^ internal_data_i[8] ^ internal_data_i[9]^ internal_data_i[10] ^ internal_data_i[14] ^ internal_data_i[15]^ internal_data_i[16]^ internal_data_i[17] ^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] ^ internal_data_i[29] ^ internal_data_i[30] ^ internal_data_i[31] : 1'b0;
+ assign parity_bits[3] = operate_i ? internal_data_i[7] ^ internal_data_i[8] ^ internal_data_i[9] ^ internal_data_i[10] ^ internal_data_i[11] ^ internal_data_i[12] ^ internal_data_i[13] ^ internal_data_i[14] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] ^ internal_data_i[26] ^ internal_data_i[27] ^ internal_data_i[28] ^ internal_data_i[29] ^ internal_data_i[30] : 1'b0;
+ //assign parity_bits[3] = operate_i ? parity_bits_i[3] ^ internal_data_i[4] ^ internal_data_i[5]^ internal_data_i[6] ^ internal_data_i[7] ^ internal_data_i[8] ^ internal_data_i[9]^ internal_data_i[10] ^ internal_data_i[18] ^ internal_data_i[19]^ internal_data_i[20]^ internal_data_i[21] ^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] : 1'b0;
+ assign parity_bits[4] = operate_i ? internal_data_i[15] ^ internal_data_i[16] ^ internal_data_i[17] ^ internal_data_i[18] ^ internal_data_i[19] ^ internal_data_i[20] ^ internal_data_i[21] ^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] ^ internal_data_i[26] ^ internal_data_i[27] ^ internal_data_i[28] ^ internal_data_i[29] ^ internal_data_i[30] : 1'b0;
+ //assign parity_bits[4] = operate_i ? parity_bits_i[4] ^ internal_data_i[11] ^ internal_data_i[12] ^ internal_data_i[13]^ internal_data_i[14] ^ internal_data_i[15] ^ internal_data_i[16] ^ internal_data_i[17]^ internal_data_i[18] ^ internal_data_i[19] ^ internal_data_i[20]^ internal_data_i[21]^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] : 1'b0;
+ assign parity_bits[5] = operate_i ? internal_data_i[31] ^ internal_data_i[32] ^ internal_data_i[33] ^ internal_data_i[34] ^ internal_data_i[35] ^ internal_data_i[36] ^ internal_data_i[37] : 1'b0;
+ //assign parity_bits[5] = operate_i ? parity_bits_i[5] ^ internal_data_i[26] ^ internal_data_i[27]^ internal_data_i[28] ^ internal_data_i[29] ^ internal_data_i[30] ^ internal_data_i[31] : 1'b0;
+ assign parity_bits[6] = operate_i ? internal_data_i[0] ^ internal_data_i[1] ^ internal_data_i[3] ^ internal_data_i[7] ^ internal_data_i[15] ^ internal_data_i[31] ^ internal_data_i[38] ^ internal_data_i[2] ^ internal_data_i[4] ^ internal_data_i[5] ^ internal_data_i[6] ^ internal_data_i[8] ^ internal_data_i[9] ^ internal_data_i[10] ^ internal_data_i[11] ^ internal_data_i[12] ^ internal_data_i[13] ^ internal_data_i[14] ^ internal_data_i[16] ^ internal_data_i[17] ^ internal_data_i[18] ^ internal_data_i[19] ^ internal_data_i[20] ^ internal_data_i[21] ^ internal_data_i[22] ^ internal_data_i[23] ^ internal_data_i[24] ^ internal_data_i[25] ^ internal_data_i[26] ^ internal_data_i[27] ^ internal_data_i[28] ^ internal_data_i[29] ^ internal_data_i[30] ^ internal_data_i[32] ^ internal_data_i[33] ^ internal_data_i[34] ^ internal_data_i[35] ^ internal_data_i[36] ^ internal_data_i[37] : 1'b0;
+ //assign parity_bits[6] = operate_i ? parity_bits_i[0] ^ parity_bits_i[1] ^ parity_bits_i[2] ^ parity_bits_i[3] ^ parity_bits_i[4] ^ parity_bits_i[5] ^ parity_bits_i[6] ^ internal_data_i[0] ^internal_data_i[1] ^ internal_data_i[2] ^ internal_data_i[3] ^ internal_data_i[4]^ internal_data_i[5] ^ internal_data_i[6]^ internal_data_i[7]^ internal_data_i[8]^ internal_data_i[9]^ internal_data_i[10] ^ internal_data_i[11]^ internal_data_i[12]^ internal_data_i[13]^ internal_data_i[14]^ internal_data_i[15]^ internal_data_i[16]^ internal_data_i[17]^ internal_data_i[18] ^ internal_data_i[19]^ internal_data_i[20]^ internal_data_i[21]^ internal_data_i[22]^ internal_data_i[23]^ internal_data_i[24]^ internal_data_i[25]^ internal_data_i[26]^ internal_data_i[27] ^ internal_data_i[28]^ internal_data_i[29]^ internal_data_i[30]^ internal_data_i[31] : 1'b0;
+
+ //assign data_representation = {internal_data_i[31],internal_data_i[30],internal_data_i[29],internal_data_i[28],internal_data_i[27],internal_data_i[26],parity_bits_i[5],internal_data_i[25],internal_data_i[24],internal_data_i[23],internal_data_i[22],internal_data_i[21],internal_data_i[20],internal_data_i[19],internal_data_i[18],internal_data_i[17],internal_data_i[16],internal_data_i[15],internal_data_i[14],internal_data_i[13],internal_data_i[12],internal_data_i[11],parity_bits_i[4],internal_data_i[10],internal_data_i[9],internal_data_i[8],internal_data_i[7],internal_data_i[6],internal_data_i[5],internal_data_i[4],parity_bits_i[3],internal_data_i[3],internal_data_i[2],internal_data_i[1],parity_bits_i[2],internal_data_i[0], parity_bits_i[1], parity_bits_i[0],1'b0};
+ assign data_representation = {internal_data_i, 1'b0};
always @(*) begin
if (operate_i == 1'b1) begin
if (parity_bits == 7'b0000000) begin
state_of_data = 2'b00;
- data_store = internal_data_i;
+ data_store = {data_representation[38],data_representation[37],data_representation[36],data_representation[35],data_representation[34],data_representation[33],data_representation[31],data_representation[30],data_representation[29],data_representation[28],data_representation[27],data_representation[26],data_representation[25],data_representation[24],data_representation[23],data_representation[22],data_representation[21],data_representation[20],data_representation[19],data_representation[18],data_representation[17],data_representation[15],data_representation[14],data_representation[13],data_representation[12],data_representation[11],data_representation[10],data_representation[9],data_representation[7],data_representation[6],data_representation[5], data_representation[3]};
valid_output = 1'b1;
end
else begin
if (parity_bits[6] == 1'b0) begin
state_of_data = 2'b10;
- data_store = internal_data_i;
+ data_store = {data_representation[38],data_representation[37],data_representation[36],data_representation[35],data_representation[34],data_representation[33],data_representation[31],data_representation[30],data_representation[29],data_representation[28],data_representation[27],data_representation[26],data_representation[25],data_representation[24],data_representation[23],data_representation[22],data_representation[21],data_representation[20],data_representation[19],data_representation[18],data_representation[17],data_representation[15],data_representation[14],data_representation[13],data_representation[12],data_representation[11],data_representation[10],data_representation[9],data_representation[7],data_representation[6],data_representation[5], data_representation[3]};
valid_output = 1'b1;
end
else begin
diff --git a/verilog/rtl/ecc_registers/parity_calculator.v b/verilog/rtl/ecc_registers/parity_calculator.v
index 9f2bea2..9ac1e46 100755
--- a/verilog/rtl/ecc_registers/parity_calculator.v
+++ b/verilog/rtl/ecc_registers/parity_calculator.v
@@ -14,22 +14,30 @@
(
input [WORD_SIZE - 1 : 0] data_to_register_i ,
input operate_i ,
- output [ECCBITS - 1 : 0] parity_bits_o ,
- output [WORD_SIZE - 1 : 0] data_to_register_o
+ output [WORD_SIZE + ECCBITS- 1 : 0] data_to_register_o
);
//***Internal logic generated by compiler***
-
+ wire intermidate_partity_bits [ECCBITS - 2 : 0];
+ reg last_bit_value;
+ reg intermidate_partity_bits_last;
//***Dumped Internal logic***
- assign parity_bits_o[0] = operate_i ? data_to_register_i[0] ^ data_to_register_i[1] ^ data_to_register_i[3] ^ data_to_register_i[4]^ data_to_register_i[6]^ data_to_register_i[8]^ data_to_register_i[10]^ data_to_register_i[11]^ data_to_register_i[13]^ data_to_register_i[15]^ data_to_register_i[17]^ data_to_register_i[19]^ data_to_register_i[21]^ data_to_register_i[23] ^ data_to_register_i[25] ^ data_to_register_i[26]^ data_to_register_i[28]^ data_to_register_i[30] : 1'b0;
- assign parity_bits_o[1] = operate_i ? data_to_register_i[0] ^ data_to_register_i[2] ^ data_to_register_i[3] ^ data_to_register_i[5]^ data_to_register_i[6]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[12]^ data_to_register_i[13]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[24] ^ data_to_register_i[25] ^ data_to_register_i[27]^ data_to_register_i[28]^ data_to_register_i[31] : 1'b0;
- assign parity_bits_o[2] = operate_i ? data_to_register_i[1] ^ data_to_register_i[2] ^ data_to_register_i[3] ^ data_to_register_i[7]^ data_to_register_i[8]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[14]^ data_to_register_i[15]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24] ^ data_to_register_i[25] ^ data_to_register_i[29]^ data_to_register_i[30]^ data_to_register_i[31] : 1'b0;
- assign parity_bits_o[3] = operate_i ? data_to_register_i[4] ^ data_to_register_i[5] ^ data_to_register_i[6] ^ data_to_register_i[7]^ data_to_register_i[8]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[18]^ data_to_register_i[19]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24] ^ data_to_register_i[25] : 1'b0;
- assign parity_bits_o[4] = operate_i ? data_to_register_i[11] ^ data_to_register_i[12] ^ data_to_register_i[13] ^ data_to_register_i[14]^ data_to_register_i[15]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[18]^ data_to_register_i[19]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24]^ data_to_register_i[25]: 1'b0;
- assign parity_bits_o[5] = operate_i ? data_to_register_i[26] ^ data_to_register_i[27] ^ data_to_register_i[28] ^ data_to_register_i[29]^ data_to_register_i[30]^ data_to_register_i[31]: 1'b0;
- assign parity_bits_o[6] = operate_i ? data_to_register_i[0] ^ data_to_register_i[1] ^ data_to_register_i[2] ^ data_to_register_i[3] ^ data_to_register_i[4]^ data_to_register_i[5]^ data_to_register_i[6]^ data_to_register_i[7]^ data_to_register_i[8]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[11]^ data_to_register_i[12]^ data_to_register_i[13]^ data_to_register_i[14]^ data_to_register_i[15]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[18]^ data_to_register_i[19]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24]^ data_to_register_i[25]^ data_to_register_i[26]^ data_to_register_i[27]^ data_to_register_i[28]^ data_to_register_i[29]^ data_to_register_i[30]^ data_to_register_i[31]: 1'b0;
- assign data_to_register_o = data_to_register_i;
+ assign intermidate_partity_bits[0] = operate_i ? data_to_register_i[0] ^ data_to_register_i[1] ^ data_to_register_i[3] ^ data_to_register_i[4]^ data_to_register_i[6]^ data_to_register_i[8]^ data_to_register_i[10]^ data_to_register_i[11]^ data_to_register_i[13]^ data_to_register_i[15]^ data_to_register_i[17]^ data_to_register_i[19]^ data_to_register_i[21]^ data_to_register_i[23] ^ data_to_register_i[25] ^ data_to_register_i[26]^ data_to_register_i[28]^ data_to_register_i[30] : 1'b0;
+ assign intermidate_partity_bits[1] = operate_i ? data_to_register_i[0] ^ data_to_register_i[2] ^ data_to_register_i[3] ^ data_to_register_i[5]^ data_to_register_i[6]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[12]^ data_to_register_i[13]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[24] ^ data_to_register_i[25] ^ data_to_register_i[27]^ data_to_register_i[28]^ data_to_register_i[31] : 1'b0;
+ assign intermidate_partity_bits[2] = operate_i ? data_to_register_i[1] ^ data_to_register_i[2] ^ data_to_register_i[3] ^ data_to_register_i[7]^ data_to_register_i[8]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[14]^ data_to_register_i[15]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24] ^ data_to_register_i[25] ^ data_to_register_i[29]^ data_to_register_i[30]^ data_to_register_i[31] : 1'b0;
+ assign intermidate_partity_bits[3] = operate_i ? data_to_register_i[4] ^ data_to_register_i[5] ^ data_to_register_i[6] ^ data_to_register_i[7]^ data_to_register_i[8]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[18]^ data_to_register_i[19]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24] ^ data_to_register_i[25] : 1'b0;
+ assign intermidate_partity_bits[4] = operate_i ? data_to_register_i[11] ^ data_to_register_i[12] ^ data_to_register_i[13] ^ data_to_register_i[14]^ data_to_register_i[15]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[18]^ data_to_register_i[19]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24]^ data_to_register_i[25]: 1'b0;
+ assign intermidate_partity_bits[5] = operate_i ? data_to_register_i[26] ^ data_to_register_i[27] ^ data_to_register_i[28] ^ data_to_register_i[29]^ data_to_register_i[30]^ data_to_register_i[31]: 1'b0;
+ //assign intermidate_partity_bits[6] = operate_i ? data_to_register_i[0] ^ data_to_register_i[1] ^ data_to_register_i[2] ^ data_to_register_i[3] ^ data_to_register_i[4]^ data_to_register_i[5]^ data_to_register_i[6]^ data_to_register_i[7]^ data_to_register_i[8]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[11]^ data_to_register_i[12]^ data_to_register_i[13]^ data_to_register_i[14]^ data_to_register_i[15]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[18]^ data_to_register_i[19]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24]^ data_to_register_i[25]^ data_to_register_i[26]^ data_to_register_i[27]^ data_to_register_i[28]^ data_to_register_i[29]^ data_to_register_i[30]^ data_to_register_i[31]: 1'b0;
+
+ always @(*) begin
+ intermidate_partity_bits_last = operate_i ? data_to_register_i[0] ^ data_to_register_i[1] ^ data_to_register_i[2] ^ data_to_register_i[3] ^ data_to_register_i[4]^ data_to_register_i[5]^ data_to_register_i[6]^ data_to_register_i[7]^ data_to_register_i[8]^ data_to_register_i[9]^ data_to_register_i[10]^ data_to_register_i[11]^ data_to_register_i[12]^ data_to_register_i[13]^ data_to_register_i[14]^ data_to_register_i[15]^ data_to_register_i[16]^ data_to_register_i[17]^ data_to_register_i[18]^ data_to_register_i[19]^ data_to_register_i[20]^ data_to_register_i[21]^ data_to_register_i[22]^ data_to_register_i[23]^ data_to_register_i[24]^ data_to_register_i[25]^ data_to_register_i[26]^ data_to_register_i[27]^ data_to_register_i[28]^ data_to_register_i[29]^ data_to_register_i[30]^ data_to_register_i[31]: 1'b0;
+ last_bit_value = intermidate_partity_bits_last ^ intermidate_partity_bits[0] ^ intermidate_partity_bits[1] ^ intermidate_partity_bits[2] ^ intermidate_partity_bits[3] ^ intermidate_partity_bits[4] ^ intermidate_partity_bits[5] ;
+ end
+ assign data_to_register_o ={last_bit_value,data_to_register_i[31],data_to_register_i[30],data_to_register_i[29],data_to_register_i[28],data_to_register_i[27],data_to_register_i[26],intermidate_partity_bits[5],data_to_register_i[25],data_to_register_i[24],data_to_register_i[23],data_to_register_i[22],data_to_register_i[21],data_to_register_i[20],data_to_register_i[19],data_to_register_i[18],data_to_register_i[17],data_to_register_i[16],data_to_register_i[15],data_to_register_i[14],data_to_register_i[13],data_to_register_i[12],data_to_register_i[11],intermidate_partity_bits[4],data_to_register_i[10],data_to_register_i[9],data_to_register_i[8],data_to_register_i[7],data_to_register_i[6],data_to_register_i[5],data_to_register_i[4],intermidate_partity_bits[3],data_to_register_i[3],data_to_register_i[2],data_to_register_i[1],intermidate_partity_bits[2],data_to_register_i[0], intermidate_partity_bits[1], intermidate_partity_bits[0]};
+
+
//***Handcrafted Internal logic***
//TODO
diff --git a/verilog/rtl/ecc_registers/register_data.v b/verilog/rtl/ecc_registers/register_data.v
index e407ae4..8d983ed 100755
--- a/verilog/rtl/ecc_registers/register_data.v
+++ b/verilog/rtl/ecc_registers/register_data.v
@@ -11,20 +11,23 @@
module register_data #(
parameter integer WORD_SIZE = 32,
parameter integer REGISTERS = 32,
- parameter integer LINE_SIZE = 128,
- parameter integer ALUOP_SIZE = 4,
parameter integer REGDIRSIZE = 5,
- parameter integer ECCBITS = 7
+ parameter integer ECCBITS = 7,
+ parameter integer WHISBONE_MASK_REGISTERS = 3
)
(
input rst_i ,
- input [WORD_SIZE - 1 : 0] data_to_register_i ,
+ input [WORD_SIZE + ECCBITS - 1 : 0] data_to_register_i ,
input [REGDIRSIZE - 1 : 0] register_i ,
+ input [WHISBONE_MASK_REGISTERS - 1 : 0] whisbone_mask_registers_i,
input wregister_i ,
input rregister_i ,
- input [ECCBITS - 1 : 0] parity_bits_i ,
- output reg [WORD_SIZE - 1 : 0] store_data_o ,
- output reg [ECCBITS - 1 : 0] parity_bits_o
+ input valid_i,
+ input [3 : 0] wstrb_i,
+ input [WORD_SIZE -1 : 0] wdata_i,
+ output reg [WORD_SIZE + ECCBITS -1: 0] store_data_o ,
+ output reg ready_o,
+ output reg [WORD_SIZE - 1 : 0] rdata_o
);
//***Internal logic generated by compiler***
@@ -35,13 +38,14 @@
reg [WORD_SIZE + ECCBITS -1:0] r[0:REGISTERS-1];
wire [ECCBITS - 1:0] parity_bits;
- assign parity_bits[0] = parity_bits_i[0];
+ /*assign parity_bits[0] = parity_bits_i[0];
assign parity_bits[1] = parity_bits_i[1];
assign parity_bits[2] = parity_bits_i[2];
assign parity_bits[3] = parity_bits_i[3];
assign parity_bits[4] = parity_bits_i[4];
assign parity_bits[5] = parity_bits_i[5];
assign parity_bits[6] = parity_bits_i[6] ^ parity_bits_i[0] ^ parity_bits_i[1] ^ parity_bits_i[2] ^ parity_bits_i[3] ^ parity_bits_i[4] ^ parity_bits_i[5] ;
+ */
//request
always @(*) begin
// calculate last parity bit
@@ -64,19 +68,26 @@
r[14] = {WORD_SIZE + ECCBITS{1'b0}};
r[15] = {WORD_SIZE + ECCBITS{1'b0}};*/
- store_data_o = {WORD_SIZE};
- parity_bits_o = {ECCBITS {1'b0}};
+ store_data_o = {WORD_SIZE + ECCBITS {1'b0}};
end
else if (rregister_i) begin
- store_data_o = r[register_i][WORD_SIZE -1:0];
- parity_bits_o = r[register_i][WORD_SIZE + ECCBITS -1: WORD_SIZE];
+ store_data_o = r[register_i];
end
else if (wregister_i) begin
// calculate parity bits
- r[register_i] = {parity_bits, data_to_register_i};
- store_data_o = {WORD_SIZE {1'b0}};
- parity_bits_o = {ECCBITS {1'b0}};
- end
+ r[register_i] = data_to_register_i;
+ //r[register_i] = {parity_bits[6], internal_data_i[31],internal_data_i[30],internal_data_i[29],internal_data_i[28],internal_data_i[27],internal_data_i[26],parity_bits[5],internal_data_i[25],internal_data_i[24],internal_data_i[23],internal_data_i[22],internal_data_i[21],internal_data_i[20],internal_data_i[19],internal_data_i[18],internal_data_i[17],internal_data_i[16],internal_data_i[15],internal_data_i[14],internal_data_i[13],internal_data_i[12],internal_data_i[11],parity_bits[4],internal_data_i[10],internal_data_i[9],internal_data_i[8],internal_data_i[7],internal_data_i[6],internal_data_i[5],internal_data_i[4],parity_bits[3],internal_data_i[3],internal_data_i[2],internal_data_i[1],parity_bits[2],internal_data_i[0], parity_bits[1], parity_bits[0]};
+ //r[register_i] = {parity_bits, data_to_register_i};
+ store_data_o = {WORD_SIZE + ECCBITS {1'b0}};
+ end
+ if (valid_i) begin
+ ready_o = 1'b1;
+ rdata_o = {r[whisbone_mask_registers_i]};
+ if (wstrb_i[0]) store_data_o[7:0] = wdata_i[7:0];
+ if (wstrb_i[1]) store_data_o[15:8] = wdata_i[15:8];
+ if (wstrb_i[2]) store_data_o[23:16] = wdata_i[23:16];
+ if (wstrb_i[3]) store_data_o[31:24] = wdata_i[31:24];
+ end
end
diff --git a/verilog/rtl/ecc_registers/register_file.v b/verilog/rtl/ecc_registers/register_file.v
index 972bf62..df3c4df 100755
--- a/verilog/rtl/ecc_registers/register_file.v
+++ b/verilog/rtl/ecc_registers/register_file.v
@@ -12,11 +12,11 @@
module register_file #(
parameter integer WORD_SIZE = 32,
- parameter integer REGISTERS = 16,
- parameter integer LINE_SIZE = 128,
- parameter integer ALUOP_SIZE = 4,
- parameter integer REGDIRSIZE = 4,
- parameter integer ECCBITS = 7
+ parameter integer REGISTERS = 32,
+ parameter integer REGDIRSIZE = 5,
+ parameter integer ECCBITS = 7,
+ parameter integer WHISBONE_MASK = 5,
+ parameter integer VERIFICATION_PINS = 2
)
(
@@ -26,13 +26,14 @@
input valid_i,
input [3:0] wstrb_i,
input [WORD_SIZE - 1 : 0] wdata_i,
+ input [WHISBONE_MASK - 1 : 0] whisbone_mask_i,
// end whishbone interface
input [WORD_SIZE - 1 : 0] data_to_register_i ,
input [REGDIRSIZE - 1 : 0] register_i ,
input wregister_i ,
input rregister_i ,
output [WORD_SIZE - 1 : 0] store_data_o ,
- output [1 : 0] operation_result_o,
+ output [VERIFICATION_PINS - 1 : 0] operation_result_o,
// whishbone interface
output ready_o,
output [WORD_SIZE - 1 : 0] rdata_o
@@ -40,11 +41,9 @@
);
//***Internal logic generated by compiler***
- wire [ECCBITS - 1 : 0] parity_bits_PCW_RD; // wiring between parity_bits_o of module PCW and parity_bits_i of module RD
- wire [WORD_SIZE - 1 : 0] data_to_register_PCW_RD; // wiring between data_to_register_o of module PCW and data_to_register_i of module RD
- wire [WORD_SIZE - 1 : 0] store_data_RD_DV; // wiring between store_data_o of module RD and internal_data_i of module DV
- wire [ECCBITS - 1 : 0] parity_bits_RD_DV; // wiring between parity_bits_o of module RD and parity_bits_i of module DV
- wire [1 : 0] operation_result_DV_PMU; // wiring between operation_result_o of module DV and operation_result_i of module PMU
+ wire [WORD_SIZE + ECCBITS- 1 : 0] data_to_register_PCW_RD; // wiring between data_to_register_o of module PCW and data_to_register_i of module RD
+ wire [WORD_SIZE + ECCBITS - 1 : 0] store_data_RD_DV; // wiring between store_data_o of module RD and internal_data_i of module DV
+ wire [VERIFICATION_PINS - 1 : 0] operation_result_DV_PMU; // wiring between operation_result_o of module DV and operation_result_i of module PMU
wire valid_output_DV_PMU; // wiring between valid_output_o of module DV and valid_output_i of module PMU
wire [WORD_SIZE - 1 : 0] store_data_DV_DO; // wiring between store_data_o of module DV and store_data_i of module DO
@@ -55,36 +54,39 @@
inst_PCW(
.data_to_register_i (data_to_register_i ),
.operate_i (wregister_i ),
- .parity_bits_o (parity_bits_PCW_RD),
.data_to_register_o (data_to_register_PCW_RD)
);
register_data #(
.WORD_SIZE (WORD_SIZE),
.REGISTERS (REGISTERS),
- .LINE_SIZE (LINE_SIZE),
- .ALUOP_SIZE (ALUOP_SIZE),
.REGDIRSIZE (REGDIRSIZE),
- .ECCBITS (ECCBITS)
+ .ECCBITS (ECCBITS),
+ .WHISBONE_MASK_REGISTERS (WHISBONE_MASK - 2)
+
)
inst_RD(
- .rst_i (rst_i ),
- .data_to_register_i (data_to_register_PCW_RD),
- .register_i (register_i ),
- .wregister_i (wregister_i ),
- .rregister_i (rregister_i ),
- .parity_bits_i (parity_bits_PCW_RD),
- .store_data_o (store_data_RD_DV),
- .parity_bits_o (parity_bits_RD_DV)
+ .rst_i (rst_i ),
+ .data_to_register_i (data_to_register_PCW_RD),
+ .register_i (register_i ),
+ .wregister_i (wregister_i ),
+ .rregister_i (rregister_i ),
+ .valid_i (valid_i),
+ .wstrb_i (wstrb_i),
+ .wdata_i (wdata_i),
+ .whisbone_mask_registers_i (whisbone_mask_i[4:2]),
+ .store_data_o (store_data_RD_DV),
+ .ready_o (ready_o),
+ .rdata_o (rdata_o)
);
data_verificator #(
.WORD_SIZE (WORD_SIZE),
- .ECCBITS (ECCBITS)
+ .ECCBITS (ECCBITS),
+ .VERIFICATION_PINS (VERIFICATION_PINS)
)
inst_DV(
.internal_data_i (store_data_RD_DV),
- .parity_bits_i (parity_bits_RD_DV),
.operate_i (rregister_i ),
.operation_result_o (operation_result_DV_PMU),
.store_data_o (store_data_DV_DO),
@@ -103,7 +105,8 @@
);
state_counters #(
- .WORD_SIZE (WORD_SIZE)
+ .WORD_SIZE (WORD_SIZE),
+ .VERIFICATION_PINS (VERIFICATION_PINS)
)
inst_PMU(
.clk_i (clk_i ),
@@ -111,6 +114,7 @@
.valid_i (valid_i),
.wstrb_i (wstrb_i),
.wdata_i (wdata_i),
+ .whisbone_mask_counter_i (whisbone_mask_i[1:0]),
.operation_result_i (operation_result_DV_PMU),
.valid_output_i (valid_output_DV_PMU),
.ready_o (ready_o),
diff --git a/verilog/rtl/ecc_registers/state_counters.v b/verilog/rtl/ecc_registers/state_counters.v
index d533966..229b0cb 100755
--- a/verilog/rtl/ecc_registers/state_counters.v
+++ b/verilog/rtl/ecc_registers/state_counters.v
@@ -9,7 +9,9 @@
//***Module***
module state_counters #(
- parameter integer WORD_SIZE = 32
+ parameter integer WORD_SIZE = 32,
+ parameter integer VERIFICATION_PINS = 2,
+ parameter integer WHISBONE_MASK_COUNTER = 2
)
(
input clk_i ,
@@ -17,7 +19,8 @@
input valid_i,
input [3 : 0] wstrb_i,
input [WORD_SIZE -1 : 0] wdata_i,
- input [1 : 0] operation_result_i ,
+ input [WHISBONE_MASK_COUNTER - 1 : 0] whisbone_mask_counter_i,
+ input [VERIFICATION_PINS - 1 : 0] operation_result_i ,
input valid_output_i,
output ready_o,
output [WORD_SIZE - 1 : 0] rdata_o
@@ -53,11 +56,33 @@
end
if (valid_i) begin
ready_o <= 1'b1;
- rdata_o = ecc_corrected_errors;
- if (wstrb_i[0]) ecc_corrected_errors[7:0] <= wdata_i[7:0];
- if (wstrb_i[1]) ecc_corrected_errors[15:8] <= wdata_i[15:8];
- if (wstrb_i[2]) ecc_corrected_errors[23:16] <= wdata_i[23:16];
- if (wstrb_i[3]) ecc_corrected_errors[31:24] <= wdata_i[31:24];
+ case (whisbone_mask_counter_i)
+ 2'b00 : begin
+ rdata_o = total_reads;
+ if (wstrb_i[0]) total_reads[7:0] <= wdata_i[7:0];
+ if (wstrb_i[1]) total_reads[15:8] <= wdata_i[15:8];
+ if (wstrb_i[2]) total_reads[23:16] <= wdata_i[23:16];
+ if (wstrb_i[3]) total_reads[31:24] <= wdata_i[31:24];
+ end
+ 2'b01: begin
+ rdata_o = ecc_corrected_errors;
+ if (wstrb_i[0]) ecc_corrected_errors[7:0] <= wdata_i[7:0];
+ if (wstrb_i[1]) ecc_corrected_errors[15:8] <= wdata_i[15:8];
+ if (wstrb_i[2]) ecc_corrected_errors[23:16] <= wdata_i[23:16];
+ if (wstrb_i[3]) ecc_corrected_errors[31:24] <= wdata_i[31:24];
+ end
+ 2'b10: begin
+ rdata_o = ecc_uncorrected_errors;
+ if (wstrb_i[0]) ecc_uncorrected_errors[7:0] <= wdata_i[7:0];
+ if (wstrb_i[1]) ecc_uncorrected_errors[15:8] <= wdata_i[15:8];
+ if (wstrb_i[2]) ecc_uncorrected_errors[23:16] <= wdata_i[23:16];
+ if (wstrb_i[3]) ecc_uncorrected_errors[31:24] <= wdata_i[31:24];
+ end
+ 2'b11: begin
+ rdata_o = {WORD_SIZE {1'b0}};
+ end
+ endcase
+
end
end
end
diff --git a/verilog/rtl/user_proj.v b/verilog/rtl/user_proj.v
index e8a66a8..2b580ec 100644
--- a/verilog/rtl/user_proj.v
+++ b/verilog/rtl/user_proj.v
@@ -38,11 +38,10 @@
module user_proj #(
parameter integer WORD_SIZE = 32,
parameter integer REGISTERS = 8,
- parameter integer LINE_SIZE = 128,
- parameter integer ALUOP_SIZE = 4,
parameter integer REGDIRSIZE = 3,
parameter integer ECCBITS = 7,
- parameter integer VERIFICATION_PINS = 2
+ parameter integer VERIFICATION_PINS = 2,
+ parameter integer WHISBONE_MASK = 5
)(
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
@@ -117,14 +116,11 @@
//assign la_write = ~la_oenb[63:32] & ~{WORD_SIZE{valid}};
assign la_data_out = {output_data, output_verification,{(127-WORD_SIZE+VERIFICATION_PINS){1'b0}}};
-
-
-
register_file #(
.WORD_SIZE (WORD_SIZE),
.REGISTERS (REGISTERS),
- .LINE_SIZE (LINE_SIZE),
- .ALUOP_SIZE (ALUOP_SIZE),
+ .WHISBONE_MASK (WHISBONE_MASK),
+ .VERIFICATION_PINS (VERIFICATION_PINS),
.REGDIRSIZE (REGDIRSIZE),
.ECCBITS (ECCBITS)
) register_file(
@@ -137,6 +133,7 @@
.register_i(la_data_in[4:2]),
.wregister_i(la_data_in[1]),
.rregister_i(la_data_in[0]),
+ .whisbone_mask_i (la_data_in[9:5]),
.store_data_o(output_data),
.operation_result_o(output_verification),
.ready_o(wbs_ack_o),
@@ -144,46 +141,4 @@
);
endmodule
-
-module counter #(
- parameter BITS = 32
-)(
- input clk,
- input reset,
- input valid,
- input [3:0] wstrb,
- input [BITS-1:0] wdata,
- input [BITS-1:0] la_write,
- input [BITS-1:0] la_input,
- output ready,
- output [BITS-1:0] rdata,
- output [BITS-1:0] count
-);
- reg ready;
- reg [BITS-1:0] count;
- reg [BITS-1:0] rdata;
-
- always @(posedge clk) begin
- if (reset) begin
- count <= 0;
- ready <= 0;
- end else begin
- ready <= 1'b0;
- if (~|la_write) begin
- count <= count + 1;
- end
- if (valid && !ready) begin
- ready <= 1'b1;
- rdata <= count;
- if (wstrb[0]) count[7:0] <= wdata[7:0];
- if (wstrb[1]) count[15:8] <= wdata[15:8];
- if (wstrb[2]) count[23:16] <= wdata[23:16];
- if (wstrb[3]) count[31:24] <= wdata[31:24];
- end else if (|la_write) begin
- count <= la_write & la_input;
- end
- end
- end
-
-endmodule
`default_nettype wire
