added test 4 for la probes, for triple redundacy full error
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 3004157..b36c250 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 la_test3 wb_port mprj_stimulus wb_test1 wb_test2 wb_test3
+PATTERNS = io_ports la_test1 la_test2 la_test3 la_test4 wb_port mprj_stimulus wb_test1 wb_test2 wb_test3
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/la_test4/Makefile b/verilog/dv/la_test4/Makefile
new file mode 100644
index 0000000..cf4d077
--- /dev/null
+++ b/verilog/dv/la_test4/Makefile
@@ -0,0 +1,78 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = la_test4
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/la_test4/la_test4.c b/verilog/dv/la_test4/la_test4.c
new file mode 100644
index 0000000..ed5f118
--- /dev/null
+++ b/verilog/dv/la_test4/la_test4.c
@@ -0,0 +1,173 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+// --------------------------------------------------------
+
+/*
+ MPRJ Logic Analyzer Test:
+ - Observes counter value through LA probes [31:0]
+ - Sets counter initial value through LA probes [63:32]
+ - Flags when counter value exceeds 500 through the management SoC gpio
+ - Outputs message to the UART when the test concludes successfuly
+*/
+int clk = 0;
+
+void clock(){
+ // clock
+ reg_la2_data = 0x00000001;
+ reg_la2_data = 0x00000000;
+ // end clock
+}
+
+void add_value_to_triplet_register(uint32_t value, uint32_t selected_register){
+
+ reg_la0_data = (selected_register << 3| 6 & 0x7);
+ reg_la1_data = value;
+}
+
+void read_value_from_triplet_register(uint32_t selected_register){
+
+ reg_la0_data = (selected_register << 3| 5 & 0x7);
+
+}
+
+void add_value_to_register(uint32_t value, uint32_t selected_register){
+
+ reg_la0_data = (selected_register << 3| 2 & 0x7);
+ reg_la1_data = value;
+}
+
+void read_value_from_register(uint32_t selected_register){
+
+ reg_la0_data = (selected_register << 3| 1 & 0x7);
+
+}
+
+void main()
+{
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ // The upper GPIO pins are configured to be output
+ // and accessble to the management SoC.
+ // Used to flad the start/end of a test
+ // The lower GPIO pins are configured to be output
+ // and accessible to the user project. They show
+ // the project count value, although this test is
+ // designed to read the project count through the
+ // logic analyzer probes.
+ // I/O 6 is configured for the UART Tx line
+
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ // Set UART clock to 64 kbaud (enable before I/O configuration)
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Configure LA probes
+ // outputs from the cpu are inputs for my project denoted for been 0
+ // inputs to the cpu are outpus for my project denoted for been 1
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
+
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB400000;
+
+ // clock and reset
+ reg_la2_data = 0x00000003;
+ reg_la2_data = 0x00000000;
+ // end clock
+
+
+ add_value_to_triplet_register(1,0);
+ clock();
+ add_value_to_register(25432,1);
+ clock();
+ add_value_to_register(38,2);
+
+ read_value_from_triplet_register(0);
+ clock();
+
+ reg_mprj_datal = 0xAB410000;
+ print("\n");
+ print("Monitor: Test 4 Passed\n\n"); // Makes simulation very long!
+ reg_mprj_datal = 0xAB510000;
+
+
+
+
+
+}
+
diff --git a/verilog/dv/la_test4/la_test4.gtkw b/verilog/dv/la_test4/la_test4.gtkw
new file mode 100644
index 0000000..47eb23e
--- /dev/null
+++ b/verilog/dv/la_test4/la_test4.gtkw
@@ -0,0 +1,40 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Fri May 28 12:06:49 2021
+[*]
+[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test4/la_test4.vcd"
+[dumpfile_mtime] "Fri May 28 12:01:29 2021"
+[dumpfile_size] 2291794024
+[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/la_test4/la_test4.gtkw"
+[timestart] 153100000
+[size] 1848 1016
+[pos] -1 -1
+*-27.000000 523712500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] la_test4_tb.
+[treeopen] la_test4_tb.uut.
+[treeopen] la_test4_tb.uut.mprj.
+[treeopen] la_test4_tb.uut.mprj.mprj.
+[sst_width] 253
+[signals_width] 310
+[sst_expanded] 1
+[sst_vpaned_height] 289
+@200
+-TOP MODULE
+@28
+la_test4_tb.uut.mprj.mprj.register_file.clk_i
+@22
+la_test4_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
+la_test4_tb.uut.mprj.mprj.register_file.register_i[4:0]
+@28
+la_test4_tb.uut.mprj.mprj.register_file.rregister_i
+la_test4_tb.uut.mprj.mprj.register_file.wregister_i
+la_test4_tb.uut.mprj.mprj.register_file.operation_type_i
+la_test4_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@22
+la_test4_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
+@200
+-GPIO
+@23
+la_test4_tb.mprj_io[37:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/verilog/dv/la_test4/la_test4_tb.v b/verilog/dv/la_test4/la_test4_tb.v
new file mode 100644
index 0000000..f49773a
--- /dev/null
+++ b/verilog/dv/la_test4/la_test4_tb.v
@@ -0,0 +1,152 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module la_test4_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ initial begin
+ $dumpfile("la_test4.vcd");
+ $dumpvars(0, la_test4_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (200) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test LA (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test LA (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(mprj_io[25:20] == 6'd0);
+ $display("LA Test 4 started");
+ //wait(mprj_io[25:20] == 6'd2);
+ wait(mprj_io[37:36] == 2'b10);
+
+ $display("LA Test 4 Finish correctly");
+ //wait(checkbits == 16'h0002);
+ #10000;
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("la_test4.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
