added read wb test to pool
diff --git a/run_test.sh b/run_test.sh
new file mode 100755
index 0000000..4f06d0c
--- /dev/null
+++ b/run_test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+make clean
+make verify-la_test1
+make verify-la_test2
+make verify-wb_test1
+make verify-wb_test2
\ No newline at end of file
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 87b0835..968ea68 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus wb_test1
+PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus wb_test1 wb_test2
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/wb_test2/Makefile b/verilog/dv/wb_test2/Makefile
new file mode 100644
index 0000000..efc74c1
--- /dev/null
+++ b/verilog/dv/wb_test2/Makefile
@@ -0,0 +1,78 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_BEHAVIOURAL_MODELS = ../
+
+## RISCV GCC
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+
+.SUFFIXES:
+
+PATTERN = wb_test2
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ $< -o $@
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/wb_test2/wb_test2.c b/verilog/dv/wb_test2/wb_test2.c
new file mode 100644
index 0000000..cd6ff89
--- /dev/null
+++ b/verilog/dv/wb_test2/wb_test2.c
@@ -0,0 +1,200 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include "verilog/dv/caravel/defs.h"
+#include "verilog/dv/caravel/stub.c"
+
+/*
+ Wishbone Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Checks counter value through the wishbone port
+*/
+void clock(){
+ // clock
+ reg_la2_data = 0x00000001;
+ reg_la2_data = 0x00000000;
+ // end clock
+}
+
+void clean_lines(){
+ reg_la0_data = 0x00000000;
+ reg_la1_data = 0x00000000;
+}
+
+void add_value_to_register(uint32_t value, uint32_t selected_regsiter){
+
+ reg_la0_data = (selected_regsiter << 2| 2 & 0x3);
+ reg_la1_data = value;
+}
+
+void read_value_from_register(uint32_t selected_regsiter){
+
+ reg_la0_data = (selected_regsiter << 2| 1 & 0x3);
+
+}
+
+#define reg_wb_register (*(volatile uint32_t*)0x30000000)
+#define reg_wb_reads (*(volatile uint32_t*)0x30000004)
+#define reg_wb_ecc_corrected (*(volatile uint32_t*)0x30000008)
+
+void main()
+{
+
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+
+ reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+
+ reg_uart_clkdiv = 625;
+ reg_uart_enable = 1;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ // Configure LA probes
+ // outputs from the cpu are inputs for my project denoted for been 0
+ // inputs to the cpu are outpus for my project denoted for been 1
+ reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
+ reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0xFFFFFFFC; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
+
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB400000;
+
+ // clock and reset
+ reg_la2_data = 0x00000003;
+ reg_la2_data = 0x00000000;
+ // end clock
+
+ add_value_to_register(1, 31);
+ clock();
+ add_value_to_register(2, 0);
+ clock();
+ add_value_to_register(3, 1);
+ clock();
+ clean_lines();
+ clock();
+ // deactivate internal clock
+ reg_la2_oenb = 0xFFFFFFFF;
+ // data 0x1
+ // partity bits 1000011
+
+ //apply modification to the register
+ reg_wb_register = 0x00000003;
+ clock();
+ // re enable clock
+ reg_la2_oenb = 0xFFFFFFFC;
+
+ read_value_from_register(31);
+ clock();
+ read_value_from_register(1);
+ clock();
+
+ clean_lines();
+ clock();
+ // deactivate internal clock
+ reg_la2_oenb = 0xFFFFFFFF;
+ // check registers file
+ if (reg_wb_reads == 0x00000002){
+ print("OK\n\n");
+ }
+ else{
+ print("ERROR\n\n");
+ }
+ if (reg_wb_ecc_corrected == 0x00000001){
+ print("OK\n\n");
+ }
+ else{
+ print("ERROR\n\n");
+ }
+
+ clock();
+ // re enable clock
+ reg_la2_oenb = 0xFFFFFFFC;
+ read_value_from_register(0);
+ clock();
+
+ reg_mprj_datal = 0xAB410000;
+ print("\n");
+ print("Monitor: Test 1 Passed\n\n"); // Makes simulation very long!
+ reg_mprj_datal = 0xAB510000;
+}
diff --git a/verilog/dv/wb_test2/wb_test2.gtkw b/verilog/dv/wb_test2/wb_test2.gtkw
new file mode 100644
index 0000000..f9d2c9f
--- /dev/null
+++ b/verilog/dv/wb_test2/wb_test2.gtkw
@@ -0,0 +1,61 @@
+[*]
+[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
+[*] Sun May 23 12:10:10 2021
+[*]
+[dumpfile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test2/wb_test2.vcd"
+[dumpfile_mtime] "Sun May 23 11:41:09 2021"
+[dumpfile_size] 1179668140
+[savefile] "/home/shuttle/core_radiation_hard/verilog/dv/wb_test2/wb_test2.gtkw"
+[timestart] 613400000
+[size] 1848 1016
+[pos] -1 -1
+*-26.000000 2444300000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] wb_test2_tb.
+[treeopen] wb_test2_tb.uut.
+[treeopen] wb_test2_tb.uut.mprj.
+[treeopen] wb_test2_tb.uut.mprj.mprj.
+[treeopen] wb_test2_tb.uut.mprj.mprj.register_file.
+[sst_width] 233
+[signals_width] 222
+[sst_expanded] 1
+[sst_vpaned_height] 289
+@200
+-TOP MODULE
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.clk_i
+wb_test2_tb.uut.mprj.mprj.register_file.rst_i
+@22
+wb_test2_tb.uut.mprj.mprj.register_file.register_i[4:0]
+wb_test2_tb.uut.mprj.mprj.register_file.data_to_register_i[31:0]
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.wregister_i
+wb_test2_tb.uut.mprj.mprj.register_file.rregister_i
+@22
+wb_test2_tb.uut.mprj.mprj.register_file.store_data_o[31:0]
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.operation_result_o[1:0]
+@200
+-
+-WB TOP
+@22
+wb_test2_tb.uut.mprj.mprj.register_file.whisbone_addr_i[31:0]
+wb_test2_tb.uut.mprj.mprj.register_file.wdata_i[31:0]
+wb_test2_tb.uut.mprj.mprj.register_file.wstrb_i[3:0]
+@28
+wb_test2_tb.uut.mprj.mprj.register_file.valid_i
+wb_test2_tb.uut.mprj.mprj.register_file.wbs_we_i
+wb_test2_tb.uut.mprj.mprj.register_file.ready_o
+@22
+wb_test2_tb.uut.mprj.mprj.register_file.rdata_o[31:0]
+@200
+-
+-GPIO
+@22
+wb_test2_tb.mprj_io[37:0]
+@200
+-
+-PMU
+@23
+wb_test2_tb.uut.mprj.mprj.register_file.inst_PMU.rdata_o[31:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/verilog/dv/wb_test2/wb_test2_tb.v b/verilog/dv/wb_test2/wb_test2_tb.v
new file mode 100644
index 0000000..1f30cf0
--- /dev/null
+++ b/verilog/dv/wb_test2/wb_test2_tb.v
@@ -0,0 +1,155 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "uprj_netlists.v"
+`include "caravel_netlists.v"
+`include "spiflash.v"
+`include "tbuart.v"
+
+module wb_test2_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+
+ reg power1, power2;
+
+ wire gpio;
+ wire uart_tx;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+
+ assign checkbits = mprj_io[31:16];
+ assign uart_tx = mprj_io[6];
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ initial begin
+ $dumpfile("wb_test2.vcd");
+ $dumpvars(0, wb_test2_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (200) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test WB (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test WB (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(mprj_io[25:20] == 6'd0);
+ $display("WB Test 2 started");
+ wait(mprj_io[25:20] == 6'd1);
+ wait(mprj_io[37:36] == 2'b01);
+ wait(mprj_io[25:20] == 6'd3);
+ wait(mprj_io[25:20] == 6'd2);
+ wait(mprj_io[37:36] == 2'b00);
+
+ $display("WB Test 2 Finish correctly");
+ //wait(checkbits == 16'h0002);
+ #10000;
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #170000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("wb_test2.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ // Testbench UART
+ tbuart tbuart (
+ .ser_rx(uart_tx)
+ );
+
+endmodule
+`default_nettype wire
