commit: f7787d700f5879a022fe12706f04b261ce77daf8
[log] [tgz]
author: Tom <tom>
Thu Jun 17 00:15:45 2021 -0700
committer: Tom <tom>
Thu Jun 17 00:15:45 2021 -0700
tree: 7b4bb7c3879bde2ae7c76453a9f32a14a406b972
parent: eebfa7c685e3fb824bac9f194d2ec53d41212b2f [diff]

Adding yaml and verilog

info.yaml[diff]
verilog/rtl/bgr.v[Added - diff]
verilog/rtl/user_analog_project_wrapper.v[diff]

3 files changed

tree: 7b4bb7c3879bde2ae7c76453a9f32a14a406b972

README.md

Caravel Analog User

:exclamation: Important Note

Please fill in your project documentation in this README.md file

:warning:	Use this sample project for analog user projects.

Refer to README for this sample project documentation.