Updating RTL to match wrapper

verilog/rtl/bgr_amp.v

diff --git a/verilog/rtl/bgr.v b/verilog/rtl/bgr_amp.v
similarity index 72%
copy from verilog/rtl/bgr.v
copy to verilog/rtl/bgr_amp.v
index 1956234..d056153 100644
--- a/verilog/rtl/bgr.v
+++ b/verilog/rtl/bgr_amp.v
@@ -20,22 +20,25 @@
  *-------------------------------------------------------------
  */
 
-module bgr
+module bgr_amp
     (
     `ifdef USE_POWER_PINS
-        inout vdda1,
-        inout vssa1,
+        inout vdd,
+        inout vss,
     `endif
-        inout vref,
-        inout ir20u
+        inout vip,
+        inout vin,
+        inout vo,
+        inout vcomp,
+        inout ir50u
     );
 
     `ifdef USE_POWER_PINS
-    assign vref  = vdda1 & ~vssa1;
-    assign ir20u = vdda1 & ~vssa1;
+    assign vo    = vdd & ~vss & ir50u &  (vip ^ vin);
+    assign vcomp = vdd & ~vss & ir50u & ~(vip ^ vin);
     `else
-    assign vref  = 1'b1;
-    assign ir20u = 1'b1;
+    assign vo    = ir50u &  (vip ^ vin);
+    assign vcomp = ir50u & ~(vip ^ vin);
     `endif
 endmodule
 

verilog/rtl/bgr_top.v

diff --git a/verilog/rtl/bgr.v b/verilog/rtl/bgr_top.v
similarity index 88%
rename from verilog/rtl/bgr.v
rename to verilog/rtl/bgr_top.v
index 1956234..6767fdf 100644
--- a/verilog/rtl/bgr.v
+++ b/verilog/rtl/bgr_top.v
@@ -20,19 +20,19 @@
  *-------------------------------------------------------------
  */
 
-module bgr
+module bgr_top
     (
     `ifdef USE_POWER_PINS
-        inout vdda1,
-        inout vssa1,
+        inout vdd,
+        inout vss,
     `endif
         inout vref,
         inout ir20u
     );
 
     `ifdef USE_POWER_PINS
-    assign vref  = vdda1 & ~vssa1;
-    assign ir20u = vdda1 & ~vssa1;
+    assign vref  = vdd & ~vss;
+    assign ir20u = vdd & ~vss;
     `else
     assign vref  = 1'b1;
     assign ir20u = 1'b1;

verilog/rtl/ldo_top.v

diff --git a/verilog/rtl/bgr.v b/verilog/rtl/ldo_top.v
similarity index 82%
copy from verilog/rtl/bgr.v
copy to verilog/rtl/ldo_top.v
index 1956234..5188a07 100644
--- a/verilog/rtl/bgr.v
+++ b/verilog/rtl/ldo_top.v
@@ -20,22 +20,21 @@
  *-------------------------------------------------------------
  */
 
-module bgr
+module ldo_top
     (
     `ifdef USE_POWER_PINS
-        inout vdda1,
-        inout vssa1,
+        inout vdd,
+        inout vss,
     `endif
+        inout vreg,
         inout vref,
-        inout ir20u
+        inout ir25u
     );
 
     `ifdef USE_POWER_PINS
-    assign vref  = vdda1 & ~vssa1;
-    assign ir20u = vdda1 & ~vssa1;
+    assign vreg = vdd & ~vss & vref & ir25u;
     `else
-    assign vref  = 1'b1;
-    assign ir20u = 1'b1;
+    assign vreg = vref & ir25u;
     `endif
 endmodule
 

verilog/rtl/pswitch_top.v

diff --git a/verilog/rtl/bgr.v b/verilog/rtl/pswitch_top.v
similarity index 79%
copy from verilog/rtl/bgr.v
copy to verilog/rtl/pswitch_top.v
index 1956234..9cf2439 100644
--- a/verilog/rtl/bgr.v
+++ b/verilog/rtl/pswitch_top.v
@@ -20,22 +20,19 @@
  *-------------------------------------------------------------
  */
 
-module bgr
+module pswitch_top
     (
     `ifdef USE_POWER_PINS
-        inout vdda1,
-        inout vssa1,
+        inout vddc,
+        inout vddp,
+        inout vss,
+        inout vddp_sw,
     `endif
-        inout vref,
-        inout ir20u
+        inout en
     );
 
     `ifdef USE_POWER_PINS
-    assign vref  = vdda1 & ~vssa1;
-    assign ir20u = vdda1 & ~vssa1;
-    `else
-    assign vref  = 1'b1;
-    assign ir20u = 1'b1;
+    assign vddp_sw = vddp & vddc & en;
     `endif
 endmodule
 

verilog/rtl/user_analog_project_wrapper.v

diff --git a/verilog/rtl/user_analog_project_wrapper.v b/verilog/rtl/user_analog_project_wrapper.v
index cbf04bc..929388d 100644
--- a/verilog/rtl/user_analog_project_wrapper.v
+++ b/verilog/rtl/user_analog_project_wrapper.v
@@ -122,7 +122,70 @@
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
-    bgr i_bgr
+    // Bandgap Ref. AMP.
+    bgr_amp i_bgr_amp
+        (
+        `ifdef USE_POWER_PINS
+            .vdd   (vdda2),
+            .vss   (vssa2),
+        `endif
+            .vip   (io_analog[8]),
+            .vin   (io_analog[9]),
+            .vo    (io_analog[7]),
+            .vcomp (io_analog[6]),
+            .ir50u (io_analog[10])
+        );
+
+
+    // load switch and LDO
+    `ifdef USE_POWER_PINS
+    wire vddp_sw;
+    `endif
+    pswitch_top i_pswitch0
+        (
+        `ifdef USE_POWER_PINS
+            .vddc    (io_analog[5]),
+            .vddp    (io_analog[4]),
+            .vss     (vssa2),
+            .vddp_sw (vddp_sw),
+        `endif
+            .en      (gpio_noesd[7])
+        );
+    pswitch_top i_pswitch1
+        (
+        `ifdef USE_POWER_PINS
+            .vddc    (io_analog[5]),
+            .vddp    (io_analog[4]),
+            .vss     (vssa2),
+            .vddp_sw (vddp_sw),
+        `endif
+            .en      (gpio_noesd[7])
+        );
+    pswitch_top i_pswitch2
+        (
+        `ifdef USE_POWER_PINS
+            .vddc    (io_analog[5]),
+            .vddp    (io_analog[4]),
+            .vss     (vssa2),
+            .vddp_sw (vddp_sw),
+        `endif
+            .en      (gpio_noesd[7])
+        );
+
+    ldo_top i_ldo
+        (
+        `ifdef USE_POWER_PINS
+            .vdd   (vddp_sw),
+            .vss   (vssa2),
+        `endif
+            .vreg  (io_analog[3]),
+            .vref  (gpio_noesd[8]),
+            .ir25u (gpio_noesd[9])
+        );
+
+
+    // Bandgap Ref.
+    bgr_top i_bgr
         (
         `ifdef USE_POWER_PINS
             .vdd   (vdda1),