commit: 3e3ad69eebb6fc0eaabfeeaa8e47b0126eb03454
[log] [tgz]
author: Ganesh Gore <goreganesh007@gmail.com>
Mon Jul 05 14:43:18 2021 -0600
committer: Ganesh Gore <goreganesh007@gmail.com>
Mon Jul 05 14:43:18 2021 -0600
tree: 0736bf7a68d47e59710fa5a149f5fcd95cbd6bf7
parent: feff2705824ab11f8852192f64699a541eb0c95b [diff]

[Verilog] Updated project files

info.yaml[diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[diff]

3 files changed

tree: 0736bf7a68d47e59710fa5a149f5fcd95cbd6bf7

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.