| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,Flow_completed,0h22m45s,0h9m13s,100412.83677009802,1.035276,20082.567354019604,20,1393.95,20791,0,0,0,0,0,0,0,178,0,-1,-1,1044135,166450,-402.95,-402.95,-377.45,-430.7,-388.57,-31867.89,-31867.89,-30061.38,-30061.38,-31103.31,865860134,0.0,25.66,23.42,0.81,0.22,-1,20568,21158,1638,2228,0,0,0,20791,880,669,492,1635,3959,3707,916,837,3622,4462,522,736,14056,0,14792,2.5089695661991622,398.57,10,AREA 0,6,20,1,153.6,153.18,0.24,0,sky130_fd_sc_hd,4,0 |
