commit	6c8c4032e0affe86a036024eaf1969ccac0ea8fb	[log] [tgz]
author	Baburaj <teche.raj2019@gmail.com>	Sun Jun 06 17:33:11 2021 +0530
committer	Baburaj <teche.raj2019@gmail.com>	Sun Jun 06 17:33:11 2021 +0530
tree	5c508cd656b324f80cb6ef4b760d05338439ddbe
parent	dd92f31d3a10ce7c0358ba4bbc8daf073bf39205 [diff]

 I2C Module from Opencores

verilog/rtl/i2c/i2c_master_bit_ctrl.v[Added - diff]
verilog/rtl/i2c/i2c_master_byte_ctrl.v[Added - diff]
verilog/rtl/i2c/i2c_master_defines.v[Added - diff]
verilog/rtl/i2c/i2c_master_top.v[Added - diff]
verilog/rtl/i2c/timescale.v[Added - diff]

5 files changed

tree: 5c508cd656b324f80cb6ef4b760d05338439ddbe

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.