Included PWM Verilog FIles

openlane/user_proj_example/config.tcl

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index caa7ec5..8386509 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -23,10 +23,14 @@
         $script_dir/../../verilog/rtl/pid/booth.v \
         $script_dir/../../verilog/rtl/pid/CLA_fixed.v \
         $script_dir/../../verilog/rtl/pid/PID.v \
+        $script_dir/../../verilog/rtl/pwm/PWM.v \
+        $script_dir/../../verilog/rtl/pwm/down_clocking_even.v \
+        $script_dir/../../verilog/rtl/pwm/down_clocking_odd.v \
+        $script_dir/../../verilog/rtl/pwm/minus_one.v \
 	$script_dir/../../verilog/rtl/user_proj_example.v"
 
 set ::env(CLOCK_PORT) ""
-set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_NET) "wb_clk_i"
 set ::env(CLOCK_PERIOD) "10"
 
 set ::env(FP_SIZING) absolute