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foss-eda-tools/third_party/shuttle/sky130/mpw-002/slot-020/0d1acf7f2df23eb2082d852ceeb6744536316124^!/.
commit
0d1acf7f2df23eb2082d852ceeb6744536316124
[log]
author
Baburaj <teche.raj2019@gmail.com>
Mon Jun 14 00:26:33 2021 +0530
committer
Baburaj <teche.raj2019@gmail.com>
Mon Jun 14 00:26:33 2021 +0530
tree
12a7c872d22d424b423c6b960c8b9134e7552ec8
parent
0b66905edf547d45178fa1e836414a8283570e17 [diff]
added SPDX-License-Identifier

diff --git a/verilog/rtl/i2c/i2c_master_bit_ctrl.v b/verilog/rtl/i2c/i2c_master_bit_ctrl.v
index 96cc325..fbca97e 100644
--- a/verilog/rtl/i2c/i2c_master_bit_ctrl.v
+++ b/verilog/rtl/i2c/i2c_master_bit_ctrl.v

@@ -32,7 +32,7 @@
 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
-////                                                             ////
+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////
 /////////////////////////////////////////////////////////////////////
 
 //  CVS Log

diff --git a/verilog/rtl/i2c/i2c_master_byte_ctrl.v b/verilog/rtl/i2c/i2c_master_byte_ctrl.v
index 613dda3..16dfb82 100644
--- a/verilog/rtl/i2c/i2c_master_byte_ctrl.v
+++ b/verilog/rtl/i2c/i2c_master_byte_ctrl.v

@@ -32,6 +32,7 @@
 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////
 ////                                                             ////
 /////////////////////////////////////////////////////////////////////
 

diff --git a/verilog/rtl/i2c/i2c_master_defines.v b/verilog/rtl/i2c/i2c_master_defines.v
index e81c546..0338aa0 100644
--- a/verilog/rtl/i2c/i2c_master_defines.v
+++ b/verilog/rtl/i2c/i2c_master_defines.v

@@ -32,6 +32,7 @@
 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////
 ////                                                             ////
 /////////////////////////////////////////////////////////////////////
 

diff --git a/verilog/rtl/i2c/i2c_master_top.v b/verilog/rtl/i2c/i2c_master_top.v
index e7c9dff..4325e4b 100644
--- a/verilog/rtl/i2c/i2c_master_top.v
+++ b/verilog/rtl/i2c/i2c_master_top.v

@@ -32,6 +32,7 @@
 //// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
 //// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////
 ////                                                             ////
 /////////////////////////////////////////////////////////////////////
 

diff --git a/verilog/rtl/i2c/timescale.v b/verilog/rtl/i2c/timescale.v
index 60d4ecb..c2dae7a 100644
--- a/verilog/rtl/i2c/timescale.v
+++ b/verilog/rtl/i2c/timescale.v

@@ -1,2 +1,3 @@
+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////
 `timescale 1ns / 10ps
 

diff --git a/verilog/rtl/pid/16x16bit_multiplier_pipelined.v b/verilog/rtl/pid/16x16bit_multiplier_pipelined.v
index 7e9f456..f0f738c 100644
--- a/verilog/rtl/pid/16x16bit_multiplier_pipelined.v
+++ b/verilog/rtl/pid/16x16bit_multiplier_pipelined.v

@@ -2,6 +2,7 @@
 Author: Zhu Xu

 Email: m99a1@yahoo.cn

 */

+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////

 

 //Booth Encoder Array

 module booth_array(


diff --git a/verilog/rtl/pid/CLA_fixed.v b/verilog/rtl/pid/CLA_fixed.v
index bd68e02..527e5c4 100644
--- a/verilog/rtl/pid/CLA_fixed.v
+++ b/verilog/rtl/pid/CLA_fixed.v

@@ -2,6 +2,7 @@
 Author: Zhu Xu

 Email: m99a1@yahoo.cn

 */

+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////

 

 module	operator_A(

 input	A,


diff --git a/verilog/rtl/pid/PID.v b/verilog/rtl/pid/PID.v
index 525f638..7416ef7 100644
--- a/verilog/rtl/pid/PID.v
+++ b/verilog/rtl/pid/PID.v

@@ -32,6 +32,7 @@
 

 

 */

+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////

 

 `define	wb_32bit

 


diff --git a/verilog/rtl/pid/booth.v b/verilog/rtl/pid/booth.v
index f33b3d8..062feab 100644
--- a/verilog/rtl/pid/booth.v
+++ b/verilog/rtl/pid/booth.v

@@ -2,6 +2,7 @@
 Author: Zhu Xu

 Email: m99a1@yahoo.cn

 */

+//// SPDX-License-Identifier: LGPL-2.1-or-later                  ////

 module booth_radix4(

 input	[2:0]codes,

 output	zero,


diff --git a/verilog/rtl/ptc/ptc_defines.v b/verilog/rtl/ptc/ptc_defines.v
index baa3a93..7e13f09 100644
--- a/verilog/rtl/ptc/ptc_defines.v
+++ b/verilog/rtl/ptc/ptc_defines.v

@@ -39,6 +39,7 @@
 //// Public License along with this source; if not, download it   ////
 //// from http://www.opencores.org/lgpl.shtml                     ////
 ////                                                              ////
+//// SPDX-License-Identifier: LGPL-2.1-or-later                   ////
 //////////////////////////////////////////////////////////////////////
 //
 // CVS Revision History

diff --git a/verilog/rtl/ptc/ptc_top.v b/verilog/rtl/ptc/ptc_top.v
index 6b81be7..4b144f0 100644
--- a/verilog/rtl/ptc/ptc_top.v
+++ b/verilog/rtl/ptc/ptc_top.v

@@ -40,6 +40,7 @@
 //// Public License along with this source; if not, download it   ////
 //// from http://www.opencores.org/lgpl.shtml                     ////
 ////                                                              ////
+//// SPDX-License-Identifier: LGPL-2.1-or-later                   ////
 //////////////////////////////////////////////////////////////////////
 //
 // CVS Revision History

diff --git a/verilog/rtl/rtc/hexmap.v b/verilog/rtl/rtc/hexmap.v
index 643ea02..15d4069 100644
--- a/verilog/rtl/rtc/hexmap.v
+++ b/verilog/rtl/rtc/hexmap.v

@@ -53,7 +53,7 @@
 // License:	GPL, v3, as defined and found on www.gnu.org,
 //		http://www.gnu.org/licenses/gpl.html
 //
-//
+//// SPDX-License-Identifier: GPL-3.0-or-later 
 ///////////////////////////////////////////////////////////////////////////
 module	hexmap(i_clk, i_hex, o_map);
 	input		i_clk;

diff --git a/verilog/rtl/rtc/rtcclock.v b/verilog/rtl/rtc/rtcclock.v
index 2099964..31877db 100644
--- a/verilog/rtl/rtc/rtcclock.v
+++ b/verilog/rtl/rtc/rtcclock.v

@@ -33,7 +33,7 @@
 // License:	GPL, v3, as defined and found on www.gnu.org,
 //		http://www.gnu.org/licenses/gpl.html
 //
-//
+//// SPDX-License-Identifier: GPL-3.0-or-later                  
 ///////////////////////////////////////////////////////////////////////////
 module	rtcclock(i_clk, 
 		// Wishbone interface

diff --git a/verilog/rtl/rtc/rtcdate.v b/verilog/rtl/rtc/rtcdate.v
index f6981c0..b41f9ae 100644
--- a/verilog/rtl/rtc/rtcdate.v
+++ b/verilog/rtl/rtc/rtcdate.v

@@ -48,7 +48,7 @@
 // License:	GPL, v3, as defined and found on www.gnu.org,
 //		http://www.gnu.org/licenses/gpl.html
 //
-//
+//// SPDX-License-Identifier: GPL-3.0-or-later 
 ///////////////////////////////////////////////////////////////////////////
 module rtcdate(i_clk, i_ppd, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
 		o_wb_ack, o_wb_stall, o_wb_data);

diff --git a/verilog/rtl/rtc/rtcgps.v b/verilog/rtl/rtc/rtcgps.v
index 8a401cc..3769ffc 100644
--- a/verilog/rtl/rtc/rtcgps.v
+++ b/verilog/rtl/rtc/rtcgps.v

@@ -37,7 +37,7 @@
 // License:	GPL, v3, as defined and found on www.gnu.org,
 //		http://www.gnu.org/licenses/gpl.html
 //
-//
+//// SPDX-License-Identifier: GPL-3.0-or-later 
 ///////////////////////////////////////////////////////////////////////////
 module	rtcgps(i_clk, 
 		// Wishbone interface

diff --git a/verilog/rtl/rtc/rtclight.v b/verilog/rtl/rtc/rtclight.v
index 51826d3..2bcb669 100644
--- a/verilog/rtl/rtc/rtclight.v
+++ b/verilog/rtl/rtc/rtclight.v

@@ -38,7 +38,7 @@
 // License:	GPL, v3, as defined and found on www.gnu.org,
 //		http://www.gnu.org/licenses/gpl.html
 //
-//
+//// SPDX-License-Identifier: GPL-3.0-or-later 
 ///////////////////////////////////////////////////////////////////////////
 module	rtclight(i_clk, 
 		// Wishbone interface