added i2c and rtc modules and related logics
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index ca5ed17..d09259c 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -21,70 +21,45 @@
$script_dir/../../caravel/verilog/rtl/defines.v \
$script_dir/../../verilog/rtl/ptc/ptc_defines.v \
$script_dir/../../verilog/rtl/ptc/ptc_top.v \
+ $script_dir/../../verilog/rtl/i2c/i2c_master_defines.v \
+ $script_dir/../../verilog/rtl/i2c/i2c_master_bit_ctrl.v \
+ $script_dir/../../verilog/rtl/i2c/i2c_master_byte_ctrl.v \
+ $script_dir/../../verilog/rtl/i2c/i2c_master_top.v \
+ $script_dir/../../verilog/rtl/rtc/hexmap.v \
+ $script_dir/../../verilog/rtl/rtc/rtcdate.v \
+ $script_dir/../../verilog/rtl/rtc/rtcgps.v \
+ $script_dir/../../verilog/rtl/rtc/rtclight.v \
+ $script_dir/../../verilog/rtl/rtc/rtcclock.v \
+ $script_dir/../../verilog/rtl/pid/16x16bit_multiplier_pipelined.v \
+ $script_dir/../../verilog/rtl/pid/booth.v \
+ $script_dir/../../verilog/rtl/pid/CLA_fixed.v \
+ $script_dir/../../verilog/rtl/pid/PID.v \
$script_dir/../../verilog/rtl/user_proj_example.v"
-
- # $script_dir/../../verilog/rtl/pid/16x16bit_multiplier_pipelined.v \
- # $script_dir/../../verilog/rtl/pid/booth.v \
- # $script_dir/../../verilog/rtl/pid/CLA_fixed.v \
- # $script_dir/../../verilog/rtl/pid/PID.v
set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) ""
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_NET) "wb_clk_i"
+set ::env(CLOCK_PERIOD) "100"
-# default 1
set ::env(DESIGN_IS_CORE) 0
-
-# default 0
set ::env(FP_PDN_CORE_RING) 0
-
-# default 6
set ::env(GLB_RT_MAXLAYER) 5
-
-# Extra settings
-
-#set ::env(FP_SIZING) absolute
-#set ::env(DIE_AREA) "0 0 900 600"
-#set ::env(DIE_AREA) [list 0.0 0.0 1748.0 1360.0]
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 24
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+4) / 100.0 ]
+set ::env(CELL_PAD) 4
-set ::env(FP_CORE_UTIL) 25
-set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
-set ::env(ROUTING_CORES) 12
+set ::env(DIODE_INSERTION_STRATEGY) 0
+#set ::env(SYNTH_STRATEGY) 2
+#set ::env(SYNTH_STRATEGY) "DELAY 1"
+set ::env(SYNTH_NO_FLAT) 0
-# default 0
-#set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(ROUTING_CORES) 16
-# default 50
-#set ::env(FP_CORE_UTIL) 20
+set ::env(MAGIC_DRC_USE_GDS) 1
+set ::env(LVS_INSERT_POWER_PINS) 1
-# default 0.55
-#set ::env(PL_TARGET_DENSITY) 0.05
-
-# If you're going to use multiple power domains, then keep this disabled.
-# default 1
-set ::env(RUN_CVC) 0
-
-# Routing Strategy 14 is more powerful than default
-# default 0
-#set ::env(ROUTING_STRATEGY) 14
-
-# Synthesis parameters
-
-# default 0
-#set ::env(SYNTH_SIZING) 1
-
-# default 1
-#set ::env(SYNTH_BUFFERING) 1
-
-# default AREA 0, try flow.tcl -synth_explore
-set ::env(SYNTH_STRATEGY) "DELAY 1"
-
-#set ::env(SYNTH_DRIVING_CELL) sky130_fd_sc_hc__inv_8
-
-# default 1
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index c64b092..81ce8b0 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,5 +1,3 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
@@ -89,75 +87,94 @@
wire [3:0] wstrb;
wire [31:0] la_write;
- wire pwm1_select , pwm2_select , pid_select ;
- wire pwm1_wbs_stb_i , pwm2_wbs_stb_i , pid_wbs_stb_i ;
- wire pwm1_wbs_ack_o , pwm2_wbs_ack_o , pid_wbs_ack_o ;
+ wire pwm1_select , pwm2_select , i2c_select , rtc_select , pid_select ;
+ wire pwm1_wbs_stb_i , pwm2_wbs_stb_i , i2c_wbs_stb_i , rtc_wbs_stb_i , pid_wbs_stb_i ;
+ wire pwm1_wbs_ack_o , pwm2_wbs_ack_o , i2c_wbs_ack_o , rtc_wbs_ack_o , pid_wbs_ack_o ;
reg [15:0] pwm1_wbs_dat_o ;
reg [15:0] pwm2_wbs_dat_o ;
+ reg [7:0] i2c_wbs_dat_o ;
+ reg [31:0] rtc_wbs_dat_o ;
reg [31:0] pid_wbs_dat_o ;
wire pwm_out1 , pwm_out2 ;
wire pwm_out1_oen , pwm_out2_oen ;
- wire ptc1_intr , ptc2_intr ;
+ wire ptc1_intr , ptc2_intr , i2c_intr , rtc_intr ;
reg led1, led2, led3 ;
wire ptc_clk1,ptc_clk2;
wire capt_in1,capt_in1;
- // Outputs
- assign io_out = {33'b0,pwm_out2,pwm_out1,led3,led2,led1};
- assign io_oeb = {33'b0,pwm_out2_oen,pwm_out1_oen,3'b111};
- //assign io_out = {35'b0,led3,led2,led1};
- //assign io_oeb = {35'b0,3'b111};
+ assign ptc_clk1 = io_in[0] ; // IO[0]
+ assign io_oeb[0]= 1'b1;
+
+ assign ptc_clk2 = io_in[1] ; // IO[1]
+ assign io_oeb[1]= 1'b1;
+
+ assign capt_in1 = io_in[2] ; // IO[2]
+ assign io_oeb[1]= 1'b1;
+
+ assign capt_in2 = io_in[3] ; // IO[3]
+ assign io_oeb[1]= 1'b1;
+
+
+ assign io_out[5:4] = la_data_in[1:0] ; // IO[5:4]
+ assign io_oeb[5:4] = la_oenb[1:0] ;
+
+ assign io_out[7:6] = {pwm_out2,pwm_out1} ; // IO[7:6]
+ assign io_oeb[7:6] = {pwm_out2_oen,pwm_out1_oen} ;
+
+ assign io_out[8] = scl_pad_o ; // IO[8]
+ assign io_oeb[8] = scl_padoen_o ;
+
+ assign i2c_scl_in = io_in[9] ; // IO[9]
+ assign io_oeb[9]= 1'b1;
+
+ assign io_out[10] = sda_pad_o ; // IO[10]
+ assign io_oeb[10] = sda_padoen_o;
+
+ assign i2c_sda_in = io_in[11] ; // IO[11]
+ assign io_oeb[11]= 1'b1;
+
// Inputs
- assign ptc_clk1 = io_in[0] ;
- assign ptc_clk2 = io_in[1] ;
- assign capt_in1 = io_in[2] ;
- assign capt_in2 = io_in[3] ;
// IRQ
- assign irq = {1'b0,ptc2_intr,ptc1_intr}; // Unused
+ assign irq = {rtc_intr , i2c_intr , {ptc2_intr || ptc1_intr} };
// LA
- //assign la_data_out = {{(127-BITS){1'b0}}, count};
- assign la_data_out = 128'b0;
- // Assuming LA probes [63:32] are for controlling the count register
- //assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
- // Assuming LA probes [65:64] are for controlling the count clk & reset
- //assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
- //assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+ assign la_data_out = 128'b0;
assign clk = wb_clk_i ;
assign rst = wb_rst_i ;
// Module Address Select Logic
assign pwm1_select = (wbs_adr_i[31:12] == 20'h30001) ;
assign pwm2_select = (wbs_adr_i[31:12] == 20'h30002) ;
+ assign i2c_select = (wbs_adr_i[31:12] == 20'h30003) ;
+ assign rtc_select = (wbs_adr_i[31:12] == 20'h30004) ;
assign pid_select = (wbs_adr_i[31:12] == 20'h30005) ;
// Module STROBE Select based on Address Range
assign pwm1_wbs_stb_i = (wbs_stb_i && pwm1_select) ;
assign pwm2_wbs_stb_i = (wbs_stb_i && pwm2_select) ;
- assign pid_wbs_stb_i = (wbs_stb_i && pid_select) ;
+ assign i2c_wbs_stb_i = (wbs_stb_i && i2c_select) ;
+ assign rtc_wbs_stb_i = (wbs_stb_i && rtc_select) ;
+ assign pid_wbs_stb_i = (wbs_stb_i && pid_select) ;
- // Led assigned from LA data in
- always @(posedge clk) begin
- led1 <= la_data_in[0] && la_oenb[0] ;
- led2 <= la_data_in[1] && la_oenb[1] ;
- led3 <= la_data_in[2] && la_oenb[2] ;
- end
// Slave Acknowledge Response
always @(posedge clk)
- wbs_ack_o <= (pwm1_wbs_ack_o || pwm2_wbs_ack_o || pid_wbs_ack_o) ;
- //wbs_ack_o <= pid_wbs_ack_o ;
+ wbs_ack_o <= (pwm1_wbs_ack_o || pwm2_wbs_ack_o || i2c_wbs_ack_o || rtc_wbs_ack_o || pid_wbs_ack_o) ;
// Slave Return Data
always @(posedge clk)
if (pwm1_wbs_ack_o)
- wbs_dat_o <= {pwm1_wbs_dat_o} ;
+ wbs_dat_o <= pwm1_wbs_dat_o ;
else if (pwm2_wbs_ack_o)
- wbs_dat_o <= {pwm2_wbs_dat_o} ;
+ wbs_dat_o <= pwm2_wbs_dat_o ;
+ else if (i2c_wbs_ack_o)
+ wbs_dat_o <= {24'b0,i2c_wbs_dat_o} ;
+ else if (rtc_wbs_ack_o)
+ wbs_dat_o <= rtc_wbs_dat_o ;
else if (pid_wbs_ack_o)
wbs_dat_o <= pid_wbs_dat_o ;
else
@@ -206,7 +223,45 @@
.oen_padoen_o (pwm_out2_oen)
);
-/*
+ // I2C Module Instanciation
+ i2c_master_top i2c_i (
+ .wb_clk_i (clk),
+ .wb_rst_i (rst),
+ .arst_i (1'b1),
+ .wb_adr_i (wbs_adr_i[2:0]), // 3-bit address
+ .wb_dat_i (wbs_dat_i[7:0]), // 8-bit data
+ .wb_dat_o (i2c_wbs_dat_o), // 8-bit data
+ .wb_we_i (wbs_we_i),
+ .wb_stb_i (rtc_wbs_stb_i),
+ .wb_cyc_i (wbs_cyc_i),
+ .wb_ack_o (i2c_wbs_ack_o),
+ .wb_inta_o (i2c_intr),
+ .scl_pad_i (i2c_scl_in),
+ .scl_pad_o (scl_pad_o),
+ .scl_padoen_o (scl_padoen_o),
+ .sda_pad_i (i2c_sda_in),
+ .sda_pad_o (sda_pad_o),
+ .sda_padoen_o (sda_padoen_o)
+ );
+
+ // RTC Module Instanciation
+
+ rtcclock rtc_i (
+ .i_clk (clk),
+ .i_wb_cyc (wbs_cyc_i),
+ .i_wb_stb (rtc_wbs_stb_i),
+ .i_wb_we (wbs_we_i),
+ .i_wb_addr (wbs_adr_i[2:0]),
+ .i_wb_data (wbs_dat_i),
+ .o_data (rtc_wbs_dat_o),
+ .o_sseg (),
+ .o_led (),
+ .o_interrupt (rtc_intr),
+ .o_ppd (),
+ .i_hack (la_data_in[2])
+ );
+
+ // PID Module Instantiation
PID pid (
.i_clk (clk),
.i_rst (rst),
@@ -220,6 +275,6 @@
.o_un (),
.o_valid ()
);
-*/
+
endmodule
`default_nettype wire
