Sign in
foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-020
/
09b3fd56f457e9bf4a92858db08c01db272f581b
commit
09b3fd56f457e9bf4a92858db08c01db272f581b
[
log
]
[
tgz
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author
Baburaj <teche.raj2019@gmail.com>
Sun Jun 06 17:26:41 2021 +0530
committer
Baburaj <teche.raj2019@gmail.com>
Sun Jun 06 17:26:41 2021 +0530
tree
1534688610c280b4a450d3a39164058408c00ec6
parent
713cb54bd7249d1875c0744906939f52e6a7e30a
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diff
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added i2c and rtc modules and related logics
openlane/user_proj_example/config.tcl
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diff
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verilog/rtl/user_proj_example.v
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diff
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2 files changed
tree: 1534688610c280b4a450d3a39164058408c00ec6
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel User Project
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.