| commit | cb2bba5043ea3ffc243b006986cfa6eb6f9f89e8 | [log] [tgz] |
|---|---|---|
| author | zainrizwankhan <65461730+zainrizwankhan@users.noreply.github.com> | Sat Jul 10 23:20:36 2021 +0500 |
| committer | GitHub <noreply@github.com> | Sat Jul 10 23:20:36 2021 +0500 |
| tree | 30f6317ef94b6e724467dccfcd17244bcfd854b2 | |
| parent | 6debc45128189f12ff0c94a564152ab46eefb936 [diff] |
Fixed bit-width mismatch in assignment
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
