added initial DV setup for Azadi SoC
diff --git a/verilog/dv/gpio/Makefile b/verilog/dv/gpio/Makefile new file mode 100644 index 0000000..89e3753 --- /dev/null +++ b/verilog/dv/gpio/Makefile
@@ -0,0 +1,78 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + +## Caravel Pointers +CARAVEL_ROOT ?= ../../../caravel +CARAVEL_PATH ?= $(CARAVEL_ROOT) +CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel +CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog +CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl +CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + +## User Project Pointers +UPRJ_VERILOG_PATH ?= ../../../verilog +UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl +UPRJ_BEHAVIOURAL_MODELS = ../ + +## RISCV GCC +GCC_PATH?=/opt/riscv32/bin +GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=/merledu1/pdks-15June/sky130A + +## Simulation mode: RTL/GL +SIM?=RTL + +.SUFFIXES: + +PATTERN = gpio + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex +ifeq ($(SIM),RTL) + iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + $< -o $@ +else + iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s + ${GCC_PATH}/${GCC_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all
diff --git a/verilog/dv/gpio/gpio.c b/verilog/dv/gpio/gpio.c new file mode 100644 index 0000000..709618f --- /dev/null +++ b/verilog/dv/gpio/gpio.c
@@ -0,0 +1,37 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +// This include is relative to $CARAVEL_PATH (see Makefile) +#include "verilog/dv/caravel/defs.h" + +// -------------------------------------------------------- + +void main() +{ + reg_spimaster_config = 0xa002; + + reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_la0_oenb = 0x00000000; + reg_la0_data = 0x0000015C; + reg_mprj_datah = 0x20; +} +
diff --git a/verilog/dv/gpio/gpio_tb.v b/verilog/dv/gpio/gpio_tb.v new file mode 100644 index 0000000..80f5925 --- /dev/null +++ b/verilog/dv/gpio/gpio_tb.v
@@ -0,0 +1,160 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire + +`timescale 1 ns / 1 ps + +`include "uprj_netlists.v" +`include "caravel_netlists.v" +`include "spiflash.v" +`include "tbprog.v" + +module gpio_tb; + // Signals declaration + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + reg prog; + + wire HIGH; + wire LOW; + wire TRI; + assign HIGH = 1'b1; + assign LOW = 1'b0; + assign TRI = 1'bz; + + wire gpio; + wire [37:0] mprj_io; + wire r_Rx_Serial; + wire mprj_ready; + + + + // Signals Assignment + //assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + assign mprj_io[5] = r_Rx_Serial; + assign mprj_io[7] = prog; + assign mprj_ready = mprj_io[37]; + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("gpio.vcd"); + $dumpvars(0, gpio_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (150) begin + repeat (1000) @(posedge clock); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed"); + $display("%c[0m",27); + //$finish; + end + + initial begin + prog <= 1'b0; + wait(mprj_ready == 1'b1); + prog <= 1'b1; + #100; + prog <= 1'b0; + $display("Monitor: gpio test Passed"); + //#10000; + //$finish; + end + + // Reset Operation + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #170000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + + spiflash #( + .FILENAME("gpio.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + + tbprog #( + .FILENAME("../hex/gpio.hex") + ) prog_uut ( + .mprj_ready (mprj_ready), + .r_Rx_Serial (r_Rx_Serial) + ); + + +endmodule +`default_nettype wire
diff --git a/verilog/dv/hex/gpio.hex b/verilog/dv/hex/gpio.hex new file mode 100644 index 0000000..6cd018d --- /dev/null +++ b/verilog/dv/hex/gpio.hex
@@ -0,0 +1,4 @@ +00158593 +FEB51CE3 +00000013 +00000FFF
diff --git a/verilog/dv/tbprog.v b/verilog/dv/tbprog.v new file mode 100644 index 0000000..6800089 --- /dev/null +++ b/verilog/dv/tbprog.v
@@ -0,0 +1,92 @@ +`timescale 1ns / 1ps + +module tbprog #( + parameter FILENAME="program.hex" +)( + input mprj_ready, + output reg r_Rx_Serial // used by task UART_WRITE_BYTE +); + +reg r_Clock = 0; +parameter c_BIT_PERIOD = 8681; // used by task UART_WRITE_BYTE +parameter c_CLOCK_PERIOD_NS = 100; + +reg [31:0] INSTR[(256*64)-1 : 0]; +integer instr_count = 0; +reg ready; +reg test; + +always @ ( posedge r_Clock ) begin + if (mprj_ready) begin + ready <= 1'b1; + end else begin + ready <= 1'b0; + end +end + +initial begin + $readmemh(FILENAME,INSTR); +end + +task UART_WRITE_BYTE; + input [7:0] i_Data; + integer ii; + begin + // Send Start Bit + r_Rx_Serial <= 1'b0; + #(c_BIT_PERIOD); + #1000; + + // Send Data Byte + for (ii=0; ii<8; ii=ii+1) begin + r_Rx_Serial <= i_Data[ii]; + #(c_BIT_PERIOD); + end + + // Send Stop Bit + r_Rx_Serial <= 1'b1; + #(c_BIT_PERIOD); + end +endtask // UART_WRITE_BYTE + +initial begin + test = 1'b0; + #1000 test = 1'b1; +end + +always + #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock; + +initial begin + r_Rx_Serial <= 1'b1; + #2000; + while (!ready && test) begin + @(posedge r_Clock) + r_Rx_Serial <= 1'b1; + end + while (instr_count<255 && INSTR[instr_count]!=32'h00000FFF) begin + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][31:24]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][23:16]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][15:8]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][7:0]); + @(posedge r_Clock); + instr_count = instr_count + 1'b1; + end + @(posedge r_Clock); + UART_WRITE_BYTE(8'h00); + @(posedge r_Clock); + UART_WRITE_BYTE(8'h00); + @(posedge r_Clock); + UART_WRITE_BYTE(8'h0F); + @(posedge r_Clock); + UART_WRITE_BYTE(8'hFF); + @(posedge r_Clock); + #1000; + $finish; +end + +endmodule
diff --git a/verilog/rtl/azadi_soc_top_caravel.v b/verilog/rtl/azadi_soc_top_caravel.v index 4c44102..f088012 100644 --- a/verilog/rtl/azadi_soc_top_caravel.v +++ b/verilog/rtl/azadi_soc_top_caravel.v
@@ -94,7 +94,7 @@ // UART assign io_oeb[5] = 1'b1; - assign io_out[2] = 1'b0; + assign io_out[5] = 1'b0; assign uart_rx = io_in[5]; assign io_oeb[6] = 1'b0; @@ -103,7 +103,7 @@ // Programming Button assign io_oeb[7] = 1'b1; - assign io_out[2] = 1'b0; + assign io_out[7] = 1'b0; assign prog = io_in[7]; // GPIO 0-18 @@ -164,7 +164,7 @@ .VGND(VGND), `endif .clk_i(wb_clk_i), - .rst_ni(wb_rst_i), + .rst_ni(~wb_rst_i), .prog(prog), // Clocks per bits
diff --git a/verilog/rtl/azadi_soc_top_dffram.v b/verilog/rtl/azadi_soc_top_dffram.v index 174a726..83d6277 100644 --- a/verilog/rtl/azadi_soc_top_dffram.v +++ b/verilog/rtl/azadi_soc_top_dffram.v
@@ -24,43 +24,26 @@ inout VPWR, // User area 1 1.8V supply inout VGND, // User area 1 digital ground `endif - clk_i, - rst_ni, - prog, - clks_per_bit, - gpio_i, - gpio_o, - gpio_oe, - uart_tx, - uart_rx, - pwm_o, - pwm_o_2, - pwm1_oe, - pwm2_oe, - ss_o, - sclk_o, - sd_o, - sd_oe, - sd_i + input wire clk_i, + input wire rst_ni, + input wire prog, + input wire [15:0] clks_per_bit, + input wire [31:0] gpio_i, + output wire [31:0] gpio_o, + output wire [31:0] gpio_oe, + output wire uart_tx, + input wire uart_rx, + output wire pwm_o, + output wire pwm_o_2, + output wire pwm1_oe, + output wire pwm2_oe, + output wire [3:0] ss_o, + output wire sclk_o, + output wire sd_o, + output wire sd_oe, + input wire sd_i ); - input wire clk_i; - input wire rst_ni; - input wire prog; - input wire [15:0] clks_per_bit; - input wire [31:0] gpio_i; - output wire [31:0] gpio_o; - output wire [31:0] gpio_oe; - output wire uart_tx; - input wire uart_rx; - output wire pwm_o; - output wire pwm_o_2; - output wire pwm1_oe; - output wire pwm2_oe; - output wire [3:0] ss_o; - output wire sclk_o; - output wire sd_o; - output wire sd_oe; - input wire sd_i; + wire prog_rst_n; wire system_rst_ni; wire [31:0] gpio_in; @@ -225,7 +208,7 @@ .sd_oe(sd_oe), .sd_i(sd_i) ); - gpio GPIO( + tl_gpio GPIO( .clk_i(clk_i), .rst_ni(system_rst_ni), .tl_i(xbarp_to_gpio), @@ -15852,7 +15835,7 @@ endcase end endmodule -module gpio ( +module tl_gpio ( clk_i, rst_ni, tl_i, @@ -22881,221 +22864,7 @@ .tl_h_o(tl_u_i[N]) ); endmodule -module tlul_socket_m1 ( - clk_i, - rst_ni, - tl_h_i, - tl_h_o, - tl_d_o, - tl_d_i -); - parameter [31:0] M = 4; - parameter [M - 1:0] HReqPass = {M {1'b1}}; - parameter [M - 1:0] HRspPass = {M {1'b1}}; - parameter [(M * 4) - 1:0] HReqDepth = {M {4'h2}}; - parameter [(M * 4) - 1:0] HRspDepth = {M {4'h2}}; - parameter [0:0] DReqPass = 1'b1; - parameter [0:0] DRspPass = 1'b1; - parameter [3:0] DReqDepth = 4'h2; - parameter [3:0] DRspDepth = 4'h2; - input wire clk_i; - input wire rst_ni; - localparam signed [31:0] tlul_pkg_TL_AIW = 8; - localparam signed [31:0] tlul_pkg_TL_AW = 32; - localparam signed [31:0] tlul_pkg_TL_DW = 32; - localparam signed [31:0] tlul_pkg_TL_DBW = 4; - localparam signed [31:0] tlul_pkg_TL_SZW = 2; - input wire [(0 >= (M - 1) ? ((2 - M) * 86) + (((M - 1) * 86) - 1) : (M * 86) - 1):(0 >= (M - 1) ? (M - 1) * 86 : 0)] tl_h_i; - localparam signed [31:0] tlul_pkg_TL_DIW = 1; - output wire [(0 >= (M - 1) ? ((2 - M) * 52) + (((M - 1) * 52) - 1) : (M * 52) - 1):(0 >= (M - 1) ? (M - 1) * 52 : 0)] tl_h_o; - output wire [85:0] tl_d_o; - input wire [51:0] tl_d_i; - localparam [31:0] IDW = tlul_pkg_TL_AIW; - localparam [31:0] STIDW = $clog2(M); - wire [(0 >= (M - 1) ? ((2 - M) * 86) + (((M - 1) * 86) - 1) : (M * 86) - 1):(0 >= (M - 1) ? (M - 1) * 86 : 0)] hreq_fifo_o; - wire [51:0] hrsp_fifo_i [0:M - 1]; - wire [M - 1:0] hrequest; - wire [M - 1:0] hgrant; - wire [85:0] dreq_fifo_i; - wire [51:0] drsp_fifo_o; - wire arb_valid; - wire arb_ready; - wire [85:0] arb_data; - generate - genvar i; - for (i = 0; i < M; i = i + 1) begin : gen_host_fifo - wire [85:0] hreq_fifo_i; - wire [STIDW - 1:0] reqid_sub; - wire [7:0] shifted_id; - assign reqid_sub = i; - assign shifted_id = {tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 69+:IDW - STIDW], reqid_sub}; - wire [7:IDW - STIDW] unused_tl_h_source; - assign unused_tl_h_source = tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 76-:STIDW]; - function automatic [2:0] sv2v_cast_3; - input reg [2:0] inp; - sv2v_cast_3 = inp; - endfunction - function automatic [1:0] sv2v_cast_539D2; - input reg [1:0] inp; - sv2v_cast_539D2 = inp; - endfunction - function automatic [7:0] sv2v_cast_F6BCE; - input reg [7:0] inp; - sv2v_cast_F6BCE = inp; - endfunction - function automatic [31:0] sv2v_cast_C6CCE; - input reg [31:0] inp; - sv2v_cast_C6CCE = inp; - endfunction - function automatic [3:0] sv2v_cast_45434; - input reg [3:0] inp; - sv2v_cast_45434 = inp; - endfunction - function automatic [31:0] sv2v_cast_486C6; - input reg [31:0] inp; - sv2v_cast_486C6 = inp; - endfunction - assign hreq_fifo_i = {tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 85], sv2v_cast_3(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 84-:3]), sv2v_cast_3(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 81-:3]), sv2v_cast_539D2(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 78-:2]), sv2v_cast_F6BCE(shifted_id), sv2v_cast_C6CCE(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 68-:32]), sv2v_cast_45434(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 36-:4]), sv2v_cast_486C6(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + tlul_pkg_TL_DW-:tlul_pkg_TL_DW]), tl_h_i[(0 >= (M - 1) ? i : (M - 1) - i) * 86]}; - tlul_fifo_sync #( - .ReqPass(HReqPass[i]), - .RspPass(HRspPass[i]), - .ReqDepth(HReqDepth[i * 4+:4]), - .RspDepth(HRspDepth[i * 4+:4]), - .SpareReqW(1) - ) u_hostfifo( - .clk_i(clk_i), - .rst_ni(rst_ni), - .tl_h_i(hreq_fifo_i), - .tl_h_o(tl_h_o[(0 >= (M - 1) ? i : (M - 1) - i) * 52+:52]), - .tl_d_o(hreq_fifo_o[(0 >= (M - 1) ? i : (M - 1) - i) * 86+:86]), - .tl_d_i(hrsp_fifo_i[i]), - .spare_req_i(1'b0), - .spare_req_o(), - .spare_rsp_i(1'b0), - .spare_rsp_o() - ); - end - endgenerate - tlul_fifo_sync #( - .ReqPass(DReqPass), - .RspPass(DRspPass), - .ReqDepth(DReqDepth), - .RspDepth(DRspDepth), - .SpareReqW(1) - ) u_devicefifo( - .clk_i(clk_i), - .rst_ni(rst_ni), - .tl_h_i(dreq_fifo_i), - .tl_h_o(drsp_fifo_o), - .tl_d_o(tl_d_o), - .tl_d_i(tl_d_i), - .spare_req_i(1'b0), - .spare_req_o(), - .spare_rsp_i(1'b0), - .spare_rsp_o() - ); - generate - for (i = 0; i < M; i = i + 1) begin : gen_arbreqgnt - assign hrequest[i] = hreq_fifo_o[((0 >= (M - 1) ? i : (M - 1) - i) * 86) + 85]; - end - endgenerate - assign arb_ready = drsp_fifo_o[0]; - localparam tlul_pkg_ArbiterImpl = "PPC"; - generate - if (tlul_pkg_ArbiterImpl == "PPC") begin : gen_arb_ppc - prim_arbiter_ppc #( - .N(M), - .DW(86), - .EnReqStabA(0) - ) u_reqarb( - .clk_i(clk_i), - .rst_ni(rst_ni), - .req_i(hrequest), - .data_i(hreq_fifo_o), - .gnt_o(hgrant), - .idx_o(), - .valid_o(arb_valid), - .data_o(arb_data), - .ready_i(arb_ready) - ); - end - else if (tlul_pkg_ArbiterImpl == "BINTREE") begin : gen_tree_arb - prim_arbiter_tree #( - .N(M), - .DW(86), - .EnReqStabA(0) - ) u_reqarb( - .clk_i(clk_i), - .rst_ni(rst_ni), - .req_i(hrequest), - .data_i(hreq_fifo_o), - .gnt_o(hgrant), - .idx_o(), - .valid_o(arb_valid), - .data_o(arb_data), - .ready_i(arb_ready) - ); - end - endgenerate - wire [M - 1:0] hfifo_rspvalid; - wire [M - 1:0] dfifo_rspready; - wire [7:0] hfifo_rspid; - wire dfifo_rspready_merged; - assign dfifo_rspready_merged = |dfifo_rspready; - function automatic [2:0] sv2v_cast_3; - input reg [2:0] inp; - sv2v_cast_3 = inp; - endfunction - function automatic [1:0] sv2v_cast_539D2; - input reg [1:0] inp; - sv2v_cast_539D2 = inp; - endfunction - function automatic [7:0] sv2v_cast_F6BCE; - input reg [7:0] inp; - sv2v_cast_F6BCE = inp; - endfunction - function automatic [31:0] sv2v_cast_C6CCE; - input reg [31:0] inp; - sv2v_cast_C6CCE = inp; - endfunction - function automatic [3:0] sv2v_cast_45434; - input reg [3:0] inp; - sv2v_cast_45434 = inp; - endfunction - function automatic [31:0] sv2v_cast_486C6; - input reg [31:0] inp; - sv2v_cast_486C6 = inp; - endfunction - assign dreq_fifo_i = {arb_valid, sv2v_cast_3(arb_data[84-:3]), sv2v_cast_3(arb_data[81-:3]), sv2v_cast_539D2(arb_data[78-:2]), sv2v_cast_F6BCE(arb_data[76-:8]), sv2v_cast_C6CCE(arb_data[68-:32]), sv2v_cast_45434(arb_data[36-:4]), sv2v_cast_486C6(arb_data[tlul_pkg_TL_DW-:tlul_pkg_TL_DW]), dfifo_rspready_merged}; - assign hfifo_rspid = {{STIDW {1'b0}}, drsp_fifo_o[42:35 + STIDW]}; - generate - for (i = 0; i < M; i = i + 1) begin : gen_idrouting - assign hfifo_rspvalid[i] = drsp_fifo_o[51] & (drsp_fifo_o[35+:STIDW] == i); - assign dfifo_rspready[i] = (hreq_fifo_o[(0 >= (M - 1) ? i : (M - 1) - i) * 86] & (drsp_fifo_o[35+:STIDW] == i)) & drsp_fifo_o[51]; - function automatic [2:0] sv2v_cast_3; - input reg [2:0] inp; - sv2v_cast_3 = inp; - endfunction - function automatic [1:0] sv2v_cast_539D2; - input reg [1:0] inp; - sv2v_cast_539D2 = inp; - endfunction - function automatic [7:0] sv2v_cast_F6BCE; - input reg [7:0] inp; - sv2v_cast_F6BCE = inp; - endfunction - function automatic [0:0] sv2v_cast_D8FDD; - input reg [0:0] inp; - sv2v_cast_D8FDD = inp; - endfunction - function automatic [31:0] sv2v_cast_486C6; - input reg [31:0] inp; - sv2v_cast_486C6 = inp; - endfunction - assign hrsp_fifo_i[i] = {hfifo_rspvalid[i], sv2v_cast_3(drsp_fifo_o[50-:3]), sv2v_cast_3(drsp_fifo_o[47-:3]), sv2v_cast_539D2(drsp_fifo_o[44-:2]), sv2v_cast_F6BCE(hfifo_rspid), sv2v_cast_D8FDD(drsp_fifo_o[34-:1]), sv2v_cast_486C6(drsp_fifo_o[33-:tlul_pkg_TL_DW]), drsp_fifo_o[1], hgrant[i]}; - end - endgenerate -endmodule + module tlul_sram_adapter ( clk_i, rst_ni,