| commit | b3bf4d444a6900dc409da387def9a4be92a847bd | [log] [tgz] |
|---|---|---|
| author | Zain Rizwan Khan <zainrizwankhan@gmail.com> | Sat Jun 26 08:57:48 2021 +0500 |
| committer | Zain Rizwan Khan <zainrizwankhan@gmail.com> | Sat Jun 26 08:57:48 2021 +0500 |
| tree | 34498cb0afd3f5903da741e071cf9416b90ebece | |
| parent | 445e0e659ee46287340d4fe2bee722a780ff6a21 [diff] |
added initial DV setup for Azadi SoC
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
