| commit | 64e9ea7090caf49ea8d6229b86e07615a00bc737 | [log] [tgz] |
|---|---|---|
| author | Zeeshan Rafique <36025181+zeeshanrafique23@users.noreply.github.com> | Sun Jun 27 00:31:21 2021 +0500 |
| committer | GitHub <noreply@github.com> | Sun Jun 27 00:31:21 2021 +0500 |
| tree | 6f313ed95910183226060bffa2cd3dfc7591e81d | |
| parent | 75f9fe87749f5631736ad0307276e8c725f11716 [diff] | |
| parent | 6390f39e50643b442e870a95d9c7b7af7840988d [diff] |
Merge pull request #5 from zainrizwankhan/submission-mpw-two made some minor changes to chip select signal
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
