| commit | 6390f39e50643b442e870a95d9c7b7af7840988d | [log] [tgz] |
|---|---|---|
| author | Zain Rizwan Khan <zainrizwankhan@gmail.com> | Sat Jun 26 17:23:28 2021 +0500 |
| committer | Zain Rizwan Khan <zainrizwankhan@gmail.com> | Sat Jun 26 17:23:28 2021 +0500 |
| tree | 11dfafab5fbf465fe592ae8b20d86b6e53db749c | |
| parent | b3bf4d444a6900dc409da387def9a4be92a847bd [diff] |
made some minor changes to chip select signal
Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found here.
