)]}'
{
  "commit": "6390f39e50643b442e870a95d9c7b7af7840988d",
  "tree": "11dfafab5fbf465fe592ae8b20d86b6e53db749c",
  "parents": [
    "b3bf4d444a6900dc409da387def9a4be92a847bd"
  ],
  "author": {
    "name": "Zain Rizwan Khan",
    "email": "zainrizwankhan@gmail.com",
    "time": "Sat Jun 26 17:23:28 2021 +0500"
  },
  "committer": {
    "name": "Zain Rizwan Khan",
    "email": "zainrizwankhan@gmail.com",
    "time": "Sat Jun 26 17:23:28 2021 +0500"
  },
  "message": "made some minor changes to chip select signal\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "83d6277883516e4fa4784eecc0606c46c2a0ca08",
      "old_mode": 33188,
      "old_path": "verilog/rtl/azadi_soc_top_dffram.v",
      "new_id": "51b05124f0412636b1c088b139b9411406c3c618",
      "new_mode": 33188,
      "new_path": "verilog/rtl/azadi_soc_top_dffram.v"
    }
  ]
}