blob: d6ce74711adfb3b6ce5fb451a04eccfa5d792460 [file] [log] [blame]
---
project:
description: "Azadi is an SoC which uses extended version of Ibex core with 'F-Extension' (RISC-V Standard Extension) for Single Precision Floating Point and limited number of peripherals."
foundry: "SkyWater"
git_url: "https://github.com/merledu/caravel_azadi_soc.git"
organization: "Micro Electronics Research Lab - Usman Institute of Technology"
organization_url: "http://merledupk.org"
owner: "MERL"
process: "SKY130"
project_name: "Azadi-SoC"
project_id: "00000051"
tags:
- "Open MPW"
- "Test Harness"
category: "Test Harness"
top_level_netlist: "caravel/verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/user_project_wrapper.v"
version: "1.00"
cover_image: "docs/source/_static/caravel_harness.png"