commit d7ccba5d306c09f9c73b0fce49c1e73b2dac428d
author zeeshanrafique23 <zeeshanrafique23@gmail.com> Mon Jun 21 19:05:48 2021 +0500
committer zeeshanrafique23 <zeeshanrafique23@gmail.com> Mon Jun 21 19:05:48 2021 +0500
tree 8a45b0e8293bfb9be29e635924f8a930f4c06a29
parent 55355ccaa856fa59654bcec462fd486f31b6403d

updated README

README.md

diff --git a/README.md b/README.md
index a666407..fe88ff1 100644
--- a/README.md
+++ b/README.md
@@ -3,4 +3,5 @@
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
 
 # Azadi RISC-V SoC
-Azadi is an SoC with 32-bit RISC-V uni-core "buraq", buraq is in-order core with a 3-stage pipeline that implements the RV32IMFD instruction set architecture.
+Azadi is an SoC with 32-bit RISC-V signal core extented version of [ibex](https://github.com/lowRISC/ibex) we named it as "buraq", it is a 3-stage pipeline core which implements the RV32IMF instruction set architecture, limited number of peripherals UART, SPI, GPIO, PWM and timer.
+The parent repository of azadi-soc can be found [here](https://github.com/merledu/azadi).