updated scripts for uprjw
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 330cf57..58f5b2f 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -13,57 +13,70 @@
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
-# Base Configurations. Don't Touch
-# section begin
set script_dir [file dirname [file normalize [info script]]]
-source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
-
set ::env(DESIGN_NAME) user_project_wrapper
-#section end
-# User Configurations
-
-## Source Verilog Files
-set ::env(VERILOG_FILES) "\
+set ::env(VERILOG_FILES) " \
$script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_project_wrapper.v"
+ $script_dir/../../verilog/rtl/user_project_wrapper.v \
+ $script_dir/../../verilog/rtl/azadi_soc_top_caravel.v\
+ $script_dir/../../verilog/rtl/azadi_soc_top_dffram.v \
+ $script_dir/../../caravel/verilog/rtl/DFFRAMBB.v \
+ $script_dir/../../verilog/rtl/DFFRAM.v "
-## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PERIOD) "40"
-## Internal Macros
-### Macro Placement
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
-
-### Black-box verilog and views
-set ::env(VERILOG_FILES_BLACKBOX) "\
- $script_dir/../../caravel/verilog/rtl/defines.v \
- $script_dir/../../verilog/rtl/user_proj_example.v"
-
-set ::env(EXTRA_LEFS) "\
- $script_dir/../../lef/user_proj_example.lef"
-
-set ::env(EXTRA_GDS_FILES) "\
- $script_dir/../../gds/user_proj_example.gds"
-
+set ::env(GLB_RT_ALLOW_CONGESTION) 1
set ::env(GLB_RT_MAXLAYER) 5
-
+set ::env(GLB_RT_MINLAYER) 2
+set ::env(GLB_RT_ADJUSTMENT) 0.45
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(FP_PDN_CHECK_NODES) 0
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+set ::env(RUN_CVC) 0
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
+# Pin Configurations. DON'T TOUCH
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3
+set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH)
+set ::env(FP_PDN_CORE_RING_VOFFSET) 14
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
new file mode 100755
index 0000000..f592f10
--- /dev/null
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1,41 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag 20th_june_fully_synthesized -overwrite
+set save_path $script_dir/../..
+
+run_yosys
+run_sta
+init_floorplan
+place_io_ol
+tap_decap_or
+run_power_grid_generation
+set ::env(YOSYS_REWRITE_VERILOG) 1
+global_placement_or
+detailed_placement_or
+run_cts
+run_routing
+write_powered_verilog -power vccd1 -ground vssd1
+set_netlist $::env(lvs_result_file_tag).powered.v
+run_magic
+run_magic_drc
+puts $::env(CURRENT_NETLIST)
+run_magic_spice_export
+
+save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(tritonRoute_result_file_tag).def \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -maglef_path $::env(magic_result_file_tag).lef.mag \
+ -spice_path $::env(magic_result_file_tag).spice \
+ -verilog_path $::env(CURRENT_NETLIST)\
+ -save_path $save_path \
+ -tag $::env(RUN_TAG)
+
+run_lvs
+run_antenna_check
+calc_total_runtime
+generate_final_summary_report
+puts_success "Flow Completed Without Fatal Errors."
+
+
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
deleted file mode 100644
index a7365ab..0000000
--- a/openlane/user_project_wrapper/macro.cfg
+++ /dev/null
@@ -1 +0,0 @@
-mprj 1175 1690 N
