updated gl netlist for 1KB DFFRAM
3 files changed
tree: 7f82ae56ac862748ac6be33e1a4f76fa8b733407
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. .gitmodules
  14. info.yaml
  15. LICENSE
  16. Makefile
  17. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

Azadi RISC-V SoC

Azadi is an SoC with 32-bit RISC-V signal core extented version of ibex we named it as “buraq”, it is a 3-stage pipeline core which implements the RV32IMF instruction set architecture, limited number of peripherals UART, SPI, GPIO, PWM and timer. The parent repository of azadi-soc can be found here.