updated the address bits
diff --git a/verilog/rtl/azadi_soc_top_dffram_4kb.v b/verilog/rtl/azadi_soc_top_dffram_4kb.v
index 80d7395..e7c6c5b 100644
--- a/verilog/rtl/azadi_soc_top_dffram_4kb.v
+++ b/verilog/rtl/azadi_soc_top_dffram_4kb.v
@@ -296,7 +296,7 @@
.EN(~instr_csb),
.Di(instr_wdata),
.Do(instr_rdata),
- .A(instr_addr[8:0])
+ .A(instr_addr[9:0])
);
data_mem_top dccm_adapter(
.clk_i(clk_i),
@@ -324,7 +324,7 @@
.EN(~data_csb),
.Di(data_wdata),
.Do(data_rdata),
- .A(data_addr[8:0])
+ .A(data_addr[9:0])
);
endmodule
module brq_core (
