added functionality for DFFRAM.

verilog/rtl/azadi_soc_top_dffram.v

diff --git a/verilog/rtl/azadi_soc_top.v b/verilog/rtl/azadi_soc_top_dffram.v
similarity index 99%
rename from verilog/rtl/azadi_soc_top.v
rename to verilog/rtl/azadi_soc_top_dffram.v
index 9f7c121..75f507d 100644
--- a/verilog/rtl/azadi_soc_top.v
+++ b/verilog/rtl/azadi_soc_top_dffram.v
@@ -263,6 +263,7 @@
 		.o_Rx_DV(rx_dv_i),
 		.o_Rx_Byte(rx_byte_i)
 	);
+
 	instr_mem_top iccm_adapter(
 		.clk_i(clk_i),
 		.rst_ni(system_rst_ni),
@@ -279,23 +280,21 @@
 		.we_o(instr_we),
 		.rdata_i(instr_rdata)
 	);
-	wire [31:0] un_conn1;
-	sky130_sram_4kbyte_1rw1r_32x1024_8 u_iccm(
-		`ifdef USE_POWER_PINS
-  	  .vccd1(VPWR),	
-  	  .vssd1(VGND),	
-  	`endif
-		.clk0(clk_i),
-		.csb0(instr_csb),
-		.web0(instr_we),
-		.wmask0(instr_wmask),
-		.addr0(instr_addr[9:0]),
-		.din0(instr_wdata),
-		.dout0(instr_rdata),
-		.clk1(1'b0),
-		.csb1(1'b1),
-		.addr1({10 {1'sb0}}),
-		.dout1(un_conn1)
+
+    wire [3:0] WE_instr;
+    assign WE_instr = instr_wmask & {4{~instr_we}};
+
+    DFFRAM u_iccm(
+	    `ifdef USE_POWER_PINS
+	        .VPWR(VPWR),
+	        .VGND(VGND),
+    	`endif
+		.CLK(clk_i),
+		.WE(WE_instr),
+		.EN(~instr_csb),
+		.Di(instr_wdata),
+		.Do(instr_rdata),
+		.A(instr_addr[7:0])
 	);
 	data_mem_top dccm_adapter(
 		.clk_i(clk_i),
@@ -309,23 +308,19 @@
 		.we_o(data_we),
 		.rdata_i(data_rdata)
 	);
-	wire [31:0] un_conn2;
-	sky130_sram_4kbyte_1rw1r_32x1024_8 u_dccm(
-		`ifdef USE_POWER_PINS
-  	  .vccd1(VPWR),	
-  	  .vssd1(VGND),	
-  	`endif
-		.clk0(clk_i),
-		.csb0(instr_csb),
-		.web0(data_we),
-		.wmask0(data_wmask),
-		.addr0(data_addr[9:0]),
-		.din0(data_wdata),
-		.dout0(data_rdata),
-		.clk1(1'b0),
-		.csb1(1'b1),
-		.addr1({10 {1'sb0}}),
-		.dout1(un_conn2)
+	wire [3:0] WE_data;
+    assign WE_data = data_wmask & {4{~data_we}};
+    DFFRAM u_dccm(
+	    `ifdef USE_POWER_PINS
+	        .VPWR(VPWR),
+	        .VGND(VGND),
+    	`endif
+		.CLK(clk_i),
+		.WE(WE_data),
+		.EN(~data_csb),
+		.Di(data_wdata),
+		.Do(data_rdata),
+		.A(data_addr[7:0])
 	);
 endmodule
 module brq_core (
@@ -23858,4 +23853,4 @@
         input csb1;
         input [ADDR_WIDTH - 1:0] addr1;
         output [DATA_WIDTH - 1:0] dout1;
-endmodule
\ No newline at end of file
+endmodule

verilog/rtl/azadi_soc_top_open.v

diff --git a/verilog/rtl/azadi_soc_top.v b/verilog/rtl/azadi_soc_top_open.v
similarity index 99%
copy from verilog/rtl/azadi_soc_top.v
copy to verilog/rtl/azadi_soc_top_open.v
index 9f7c121..87a6822 100644
--- a/verilog/rtl/azadi_soc_top.v
+++ b/verilog/rtl/azadi_soc_top_open.v
@@ -316,7 +316,7 @@
   	  .vssd1(VGND),	
   	`endif
 		.clk0(clk_i),
-		.csb0(instr_csb),
+		.csb0(data_csb),
 		.web0(data_we),
 		.wmask0(data_wmask),
 		.addr0(data_addr[9:0]),
@@ -23858,4 +23858,4 @@
         input csb1;
         input [ADDR_WIDTH - 1:0] addr1;
         output [DATA_WIDTH - 1:0] dout1;
-endmodule
\ No newline at end of file
+endmodule