corrected power pin issue counter during LVS check
diff --git a/gds/azadi_soc_top_caravel.gds b/gds/azadi_soc_top_caravel.gds
new file mode 100644
index 0000000..e05b12d
--- /dev/null
+++ b/gds/azadi_soc_top_caravel.gds
Binary files differ
diff --git a/gds/azadi_soc_top_caravel.gds.gz b/gds/azadi_soc_top_caravel.gds.gz
deleted file mode 100644
index 7dddec3..0000000
--- a/gds/azadi_soc_top_caravel.gds.gz
+++ /dev/null
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
new file mode 100644
index 0000000..1950543
--- /dev/null
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
deleted file mode 100644
index 286a0cb..0000000
--- a/gds/user_project_wrapper.gds.gz
+++ /dev/null
Binary files differ
diff --git a/verilog/rtl/azadi_soc_top_caravel.v b/verilog/rtl/azadi_soc_top_caravel.v
index 02c1527..cea49fb 100644
--- a/verilog/rtl/azadi_soc_top_caravel.v
+++ b/verilog/rtl/azadi_soc_top_caravel.v
@@ -4,14 +4,8 @@
module azadi_soc_top_caravel (
`ifdef USE_POWER_PINS
- inout vdda1, // User area 1 3.3V supply
- inout vdda2, // User area 2 3.3V supply
- inout vssa1, // User area 1 analog ground
- inout vssa2, // User area 2 analog ground
- inout vccd1, // User area 1 1.8V supply
- inout vccd2, // User area 2 1.8v supply
- inout vssd1, // User area 1 digital ground
- inout vssd2, // User area 2 digital ground
+ inout VPWR,
+ inout VGND,
`endif
// Wishbone Slave ports (WB MI A)
@@ -150,8 +144,8 @@
azadi_soc_top soc_top(
`ifdef USE_POWER_PINS
- .VPWR(vccd1),
- .VGND(vssd1),
+ .VPWR(VPWR),
+ .VGND(VGND),
`endif
.clk_i(wb_clk_i),
.rst_ni(wb_rst_i),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 7695b2e..a64238d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -79,15 +79,9 @@
);
azadi_soc_top_caravel mprj(
- `ifdef USE_POWER_PINS
- .vdda1(vdda1),
- .vdda2(vdda2),
- .vssa1(vssa1),
- .vssa2(vssa2),
- .vccd1(vccd1),
- .vccd2(vccd2),
- .vssd1(vssd1),
- .vssd2(vssd2),
+ `ifdef USE_POWER_PINS
+ .VPWR(vccd1), // User area 1 1.8V power
+ .VGND(vssd1), // User area 1 digital ground
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
