commit	7f8fd807cd6b1de05a43b82c9f3b3039c25bc092	[log] [tgz]
author	zeeshanrafique23 <zeeshanrafique23@gmail.com>	Mon Jun 21 11:06:51 2021 +0500
committer	zeeshanrafique23 <zeeshanrafique23@gmail.com>	Mon Jun 21 11:06:51 2021 +0500
tree	42d2d15ecae2e56ef13fc4243fcd86b8242ea741
parent	61ec7aaa40973f0decc3e3a6b5b65dfdc046e35c [diff]

corrected power pin issue counter during LVS check

gds/azadi_soc_top_caravel.gds[Added - diff]
gds/azadi_soc_top_caravel.gds.gz[Deleted - diff]
gds/user_project_wrapper.gds[Added - diff]
gds/user_project_wrapper.gds.gz[Deleted - diff]
verilog/rtl/azadi_soc_top_caravel.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

6 files changed

tree: 42d2d15ecae2e56ef13fc4243fcd86b8242ea741

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md

README.md

Caravel User Project

Azadi RISC-V SoC

Azadi is an SoC with 32-bit RISC-V uni-core “buraq”, buraq is in-order core with a 3-stage pipeline that implements the RV32IMFD instruction set architecture.