corrected power pin issue counter during LVS check
6 files changed
tree: 42d2d15ecae2e56ef13fc4243fcd86b8242ea741
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. .gitmodules
  14. info.yaml
  15. LICENSE
  16. Makefile
  17. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

Azadi RISC-V SoC

Azadi is an SoC with 32-bit RISC-V uni-core “buraq”, buraq is in-order core with a 3-stage pipeline that implements the RV32IMFD instruction set architecture.