commit 70e5ba252f51bc3541e3b3d695cca3c50de59b64
author zeeshanrafique23 <zeeshanrafique23@gmail.com> Mon Jul 26 17:10:00 2021 +0100
committer zeeshanrafique23 <zeeshanrafique23@gmail.com> Mon Jul 26 17:10:00 2021 +0100
tree ac83b21c5b90d793eddf36e9aed6c388991d7681
parent 6e9cb0ca159d15061a25ee9f714c17a7a0c86ffa
parent dcf994f2e93c85a43862c1d7bcbbc137c5af97c4

Merge branch 'main' of https://github.com/Muhd-Waleed/caravel_user_project into test

README.md

diff --git a/README.md b/README.md
index f6af6a9..394de18 100644
--- a/README.md
+++ b/README.md
@@ -19,8 +19,6 @@
 
 [![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
 
-# Azadi RISC-V SoC
-Azadi is an SoC with a 32-bit RISC-V signal core extended version of [ibex](https://github.com/lowRISC/ibex) we named it "buraq", it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer. The parent repository of azadi-soc can be found [here](https://github.com/merledu/azadi).
+# Uqab RISC-V SoC
+Uqab is an SoC which hold 32-bit RISCV based processor and have peripherals (Pulse Width Modulation (PWM) ,Serial Peripheral Interface (SPI),General Purpose Input Output  (GPIO), and Timer)
 
-## Azadi SoC DFFRAM: Flattened with user_project_wrapper
-![azadi-gds](images/gds.png)