commit 5b47047e46d7104ea0bbdcc16c17f310d38854dd
author zeeshanrafique23 <zeeshanrafique23@gmail.com> Tue Jun 22 11:56:22 2021 +0500
committer zeeshanrafique23 <zeeshanrafique23@gmail.com> Tue Jun 22 11:56:22 2021 +0500
tree 15fa8efc65b9acf77d79edafac945dc739430a30
parent c581a125d2e933ac47d7ead237200bc4c17fa5af

added image of gds

README.md

diff --git a/README.md b/README.md
index 02f0aa9..94e35a8 100644
--- a/README.md
+++ b/README.md
@@ -6,5 +6,5 @@
 Azadi is an SoC with 32-bit RISC-V signal core extented version of [ibex](https://github.com/lowRISC/ibex) we named it as "buraq", it is a 3-stage pipeline core which implements the RV32IMF instruction set architecture, limited number of peripherals UART, SPI, GPIO, PWM and timer.
 The parent repository of azadi-soc can be found [here](https://github.com/merledu/azadi).
 
-# Azadi SoC DFFRAM: Flattened with user_project_wrapper
+## Azadi SoC DFFRAM: Flattened with user_project_wrapper
 ![azadi-gds](images/gds.png)