renamed power and ground pins for DFFRAM

verilog/rtl/azadi_soc_top_dffram.v

diff --git a/verilog/rtl/azadi_soc_top_dffram.v b/verilog/rtl/azadi_soc_top_dffram.v
index 75f507d..3e3ceb4 100644
--- a/verilog/rtl/azadi_soc_top_dffram.v
+++ b/verilog/rtl/azadi_soc_top_dffram.v
@@ -3,8 +3,8 @@
 `default_nettype wire
 module azadi_soc_top (
 	`ifdef USE_POWER_PINS
-    inout VPWR,	// User area 1 1.8V supply
-    inout VGND,	// User area 1 digital ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
   `endif
 	clk_i,
 	rst_ni,
@@ -286,8 +286,8 @@
 
     DFFRAM u_iccm(
 	    `ifdef USE_POWER_PINS
-	        .VPWR(VPWR),
-	        .VGND(VGND),
+	        .VPWR(vccd1),
+	        .VGND(vssd1),
     	`endif
 		.CLK(clk_i),
 		.WE(WE_instr),
@@ -312,8 +312,8 @@
     assign WE_data = data_wmask & {4{~data_we}};
     DFFRAM u_dccm(
 	    `ifdef USE_POWER_PINS
-	        .VPWR(VPWR),
-	        .VGND(VGND),
+	        .VPWR(vccd1),
+	        .VGND(vssd1),
     	`endif
 		.CLK(clk_i),
 		.WE(WE_data),