| commit | 44d96cff4c0bafc977da2ad71a5f2a60ad863bcc | [log] [tgz] |
|---|---|---|
| author | zeeshanrafique23 <zeeshanrafique23@gmail.com> | Wed Jun 02 18:17:21 2021 +0500 |
| committer | zeeshanrafique23 <zeeshanrafique23@gmail.com> | Wed Jun 02 18:17:21 2021 +0500 |
| tree | 1aa04c05eafbe812d044f6c5bb6c52dae2dd1e15 | |
| parent | 18bdbbe552f030a5087e8766e1568506c94d14d2 [diff] |
added instance for azadi_soc top caravel
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 2a3462b..524b489 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -82,7 +82,7 @@ /* User project is instantiated here */ /*--------------------------------------*/ -user_proj_example mprj ( +azadi_soc_top_caravel mprj ( `ifdef USE_POWER_PINS .vdda1(vdda1), // User area 1 3.3V power .vdda2(vdda2), // User area 2 3.3V power