resolve the mismatch in directionality of cell port issue
diff --git a/verilog/rtl/azadi_soc_top_caravel.v b/verilog/rtl/azadi_soc_top_caravel.v
index 686626d..56b1e0e 100644
--- a/verilog/rtl/azadi_soc_top_caravel.v
+++ b/verilog/rtl/azadi_soc_top_caravel.v
@@ -109,6 +109,7 @@
// UART
assign io_oeb[5] = 1'b1;
+ assign io_out[2] = 1'b0;
assign uart_rx = io_in[5];
assign io_oeb[6] = 1'b0;
@@ -116,6 +117,7 @@
// Programming Button
assign io_oeb[7] = 1'b1;
+ assign io_out[2] = 1'b0;
assign prog = io_in[7];
// GPIO 0-18
@@ -167,7 +169,6 @@
assign io_out[37:35] = gpio_o [29:27];
// Logic Analyzer ports
- assign la_oenb[15:0] = 16'hffff;
assign clks_per_bit = la_data_in[15:0];
azadi_soc_top soc_top(
