removed unused wire & flops
diff --git a/verilog/rtl/brq_core.sv b/verilog/rtl/brq_core.sv index 1e83243..b42e487 100644 --- a/verilog/rtl/brq_core.sv +++ b/verilog/rtl/brq_core.sv
@@ -33,7 +33,7 @@ input logic clk_i, input logic rst_ni, - input logic test_en_i, // enable all clock gates for testing + // input logic test_en_i, // enable all clock gates for testing input logic [31:0] hart_id_i, input logic [31:0] boot_addr_i, @@ -102,7 +102,8 @@ output logic alert_major_o, output logic core_sleep_o ); - +logic test_en_i; +assign test_en_i = 1'b0; import brq_pkg::*; // floating point @@ -174,7 +175,7 @@ logic [15:0] instr_rdata_c_id; // Compressed instruction sampled inside IF stage logic instr_is_compressed_id; logic instr_perf_count_id; - logic instr_bp_taken_id; + // logic instr_bp_taken_id; logic instr_fetch_err; // Bus error on instr fetch logic instr_fetch_err_plus2; // Instruction error is misaligned logic illegal_c_insn_id; // Illegal compressed instruction sent to ID stage @@ -199,7 +200,7 @@ logic instr_valid_clear; logic pc_set; logic pc_set_spec; - logic nt_branch_mispredict; + //logic nt_branch_mispredict; pc_sel_e pc_mux_id; // Mux selector for next PC exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC exc_cause_e exc_cause; // Exception cause @@ -276,7 +277,7 @@ // with wrong priviledge level, // or missing write permissions - // Data Memory Control + // Data Memory Controlpc_mismatch_alert_o logic lsu_we; logic [1:0] lsu_type; logic lsu_sign_ext; @@ -470,11 +471,11 @@ .instr_rdata_alu_id_o ( instr_rdata_alu_id ), .instr_rdata_c_id_o ( instr_rdata_c_id ), .instr_is_compressed_id_o ( instr_is_compressed_id ), - .instr_bp_taken_o ( instr_bp_taken_id ), + // .instr_bp_taken_o ( instr_bp_taken_id ), .instr_fetch_err_o ( instr_fetch_err ), .instr_fetch_err_plus2_o ( instr_fetch_err_plus2 ), .illegal_c_insn_id_o ( illegal_c_insn_id ), - .dummy_instr_id_o ( dummy_instr_id ), + //.dummy_instr_id_o ( dummy_instr_id ), .pc_if_o ( pc_if ), .pc_id_o ( pc_id ), @@ -483,15 +484,15 @@ .pc_set_i ( pc_set ), .pc_set_spec_i ( pc_set_spec ), .pc_mux_i ( pc_mux_id ), - .nt_branch_mispredict_i ( nt_branch_mispredict ), + // .nt_branch_mispredict_i ( nt_branch_mispredict ), .exc_pc_mux_i ( exc_pc_mux_id ), - .exc_cause ( exc_cause ), - .dummy_instr_en_i ( dummy_instr_en ), - .dummy_instr_mask_i ( dummy_instr_mask ), - .dummy_instr_seed_en_i ( dummy_instr_seed_en ), - .dummy_instr_seed_i ( dummy_instr_seed ), - .icache_enable_i ( icache_enable ), - .icache_inval_i ( icache_inval ), + // .exc_cause ( exc_cause ), + // .dummy_instr_en_i ( dummy_instr_en ), + // .dummy_instr_mask_i ( dummy_instr_mask ), + // .dummy_instr_seed_en_i ( dummy_instr_seed_en ), + // .dummy_instr_seed_i ( dummy_instr_seed ), + // .icache_enable_i ( icache_enable ), + // .icache_inval_i ( icache_inval ), // branch targets .branch_target_ex_i ( branch_target_ex ), @@ -542,7 +543,7 @@ .instr_rdata_alu_i ( instr_rdata_alu_id ), .instr_rdata_c_i ( instr_rdata_c_id ), .instr_is_compressed_i ( instr_is_compressed_id ), - .instr_bp_taken_i ( instr_bp_taken_id ), + //.instr_bp_taken_i ( instr_bp_taken_id ), // Jumps and branches .branch_decision_i ( branch_decision ), @@ -555,7 +556,7 @@ .pc_set_o ( pc_set ), .pc_set_spec_o ( pc_set_spec ), .pc_mux_o ( pc_mux_id ), - .nt_branch_mispredict_o ( nt_branch_mispredict ), + //.nt_branch_mispredict_o ( nt_branch_mispredict ), .exc_pc_mux_o ( exc_pc_mux_id ), .exc_cause_o ( exc_cause ), .icache_inval_o ( icache_inval ), @@ -923,7 +924,7 @@ .clk_i ( clk_i ), .rst_ni ( rst_ni ), - .test_en_i ( test_en_i ), + // .test_en_i ( test_en_i ), .dummy_instr_id_i ( dummy_instr_id ), .raddr_a_i ( rf_raddr_a ), @@ -1132,11 +1133,11 @@ .pc_wb_i ( pc_wb ), .data_ind_timing_o ( data_ind_timing ), - .dummy_instr_en_o ( dummy_instr_en ), - .dummy_instr_mask_o ( dummy_instr_mask ), - .dummy_instr_seed_en_o ( dummy_instr_seed_en ), - .dummy_instr_seed_o ( dummy_instr_seed ), - .icache_enable_o ( icache_enable ), + // .dummy_instr_en_o ( dummy_instr_en ), + // .dummy_instr_mask_o ( dummy_instr_mask ), + // .dummy_instr_seed_en_o ( dummy_instr_seed_en ), + // .dummy_instr_seed_o ( dummy_instr_seed ), + // .icache_enable_o ( icache_enable ), .csr_shadow_err_o ( csr_shadow_err ), .csr_save_if_i ( csr_save_if ),
diff --git a/verilog/rtl/brq_core_top.sv b/verilog/rtl/brq_core_top.sv index 65b428a..93079df 100644 --- a/verilog/rtl/brq_core_top.sv +++ b/verilog/rtl/brq_core_top.sv
@@ -34,7 +34,7 @@ input tlul_pkg::tl_d2h_t tl_d_i, output tlul_pkg::tl_h2d_t tl_d_o, - input logic test_en_i, // enable all clk_i gates for testing + // input logic test_en_i, // enable all clk_i gates for testing input logic [31:0] hart_id_i, input logic [31:0] boot_addr_i, @@ -105,7 +105,7 @@ .clk_i (clk_i), .rst_ni(rst_ni), - .test_en_i (test_en_i), // enable all clk_i gates for testing + // .test_en_i (test_en_i), // enable all clk_i gates for testing .hart_id_i (hart_id_i), .boot_addr_i(boot_addr_i),
diff --git a/verilog/rtl/brq_cs_registers.sv b/verilog/rtl/brq_cs_registers.sv index 6b33279..39c7967 100644 --- a/verilog/rtl/brq_cs_registers.sv +++ b/verilog/rtl/brq_cs_registers.sv
@@ -79,11 +79,6 @@ // CPU control bits output logic data_ind_timing_o, - output logic dummy_instr_en_o, - output logic [2:0] dummy_instr_mask_o, - output logic dummy_instr_seed_en_o, - output logic [31:0] dummy_instr_seed_o, - output logic icache_enable_o, output logic csr_shadow_err_o, // Exception save/restore @@ -120,6 +115,12 @@ import brq_pkg::*; import fpnew_pkg::roundmode_e; + logic dummy_instr_en_o; + logic [2:0] dummy_instr_mask_o; + logic dummy_instr_seed_en_o; + logic [31:0] dummy_instr_seed_o; + logic icache_enable_o; + localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1; localparam int unsigned PMPAddrWidth = (PMPGranularity > 0) ? 33 - PMPGranularity : 32; @@ -797,7 +798,23 @@ //////////////////////// // CSR instantiations // //////////////////////// - + logic unused_error1; + logic unused_error2; + logic unused_error3; + logic unused_error4; + logic unused_error5; + logic unused_error6; + logic unused_error7; + logic unused_error8; + logic unused_error9; + logic unused_error10; + logic unused_error11; + logic unused_error12; + logic unused_error13; + logic unused_error14; + logic unused_error15; + logic unused_error16; + logic unused_error17; // MSTATUS localparam status_t MSTATUS_RST_VAL = '{mie: 1'b0, mpie: 1'b1, @@ -829,7 +846,7 @@ .wr_data_i (fflag_wdata), .wr_en_i (fflags_en | is_fp_instr_i), .rd_data_o (fflags_q), - .rd_error_o () + .rd_error_o (unused_error1) ); // FRM @@ -843,7 +860,7 @@ .wr_data_i (frm_d), .wr_en_i (frm_en), .rd_data_o (frm_q), - .rd_error_o () + .rd_error_o (unused_error2) ); // MEPC @@ -857,7 +874,7 @@ .wr_data_i (mepc_d), .wr_en_i (mepc_en), .rd_data_o (mepc_q), - .rd_error_o () + .rd_error_o (unused_error3) ); // MIE @@ -875,7 +892,7 @@ .wr_data_i ({mie_d}), .wr_en_i (mie_en), .rd_data_o (mie_q), - .rd_error_o () + .rd_error_o (unused_error4) ); // MSCRATCH @@ -889,7 +906,7 @@ .wr_data_i (csr_wdata_int), .wr_en_i (mscratch_en), .rd_data_o (mscratch_q), - .rd_error_o () + .rd_error_o (unused_error5) ); // MCAUSE @@ -903,7 +920,7 @@ .wr_data_i (mcause_d), .wr_en_i (mcause_en), .rd_data_o (mcause_q), - .rd_error_o () + .rd_error_o (unused_error6) ); // MTVAL @@ -917,7 +934,7 @@ .wr_data_i (mtval_d), .wr_en_i (mtval_en), .rd_data_o (mtval_q), - .rd_error_o () + .rd_error_o (unused_error7) ); // MTVEC @@ -951,7 +968,7 @@ .wr_data_i ({dcsr_d}), .wr_en_i (dcsr_en), .rd_data_o (dcsr_q), - .rd_error_o () + .rd_error_o (unused_error8) ); // DEPC @@ -965,7 +982,7 @@ .wr_data_i (depc_d), .wr_en_i (depc_en), .rd_data_o (depc_q), - .rd_error_o () + .rd_error_o (unused_error9) ); // DSCRATCH0 @@ -979,7 +996,7 @@ .wr_data_i (csr_wdata_int), .wr_en_i (dscratch0_en), .rd_data_o (dscratch0_q), - .rd_error_o () + .rd_error_o (unused_error10) ); // DSCRATCH1 @@ -993,7 +1010,7 @@ .wr_data_i (csr_wdata_int), .wr_en_i (dscratch1_en), .rd_data_o (dscratch1_q), - .rd_error_o () + .rd_error_o (unused_error11) ); // MSTACK @@ -1011,7 +1028,7 @@ .wr_data_i ({mstack_d}), .wr_en_i (mstack_en), .rd_data_o (mstack_q), - .rd_error_o () + .rd_error_o (unused_error12) ); // MSTACK_EPC @@ -1025,7 +1042,7 @@ .wr_data_i (mstack_epc_d), .wr_en_i (mstack_en), .rd_data_o (mstack_epc_q), - .rd_error_o () + .rd_error_o (unused_error13) ); // MSTACK_CAUSE @@ -1039,7 +1056,7 @@ .wr_data_i (mstack_cause_d), .wr_en_i (mstack_en), .rd_data_o (mstack_cause_q), - .rd_error_o () + .rd_error_o (unused_error14) ); // ----------------- @@ -1357,7 +1374,7 @@ .wr_data_i (tselect_d), .wr_en_i (tselect_we), .rd_data_o (tselect_q), - .rd_error_o () + .rd_error_o (unused_error15) ); for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_reg @@ -1371,7 +1388,7 @@ .wr_data_i (tmatch_control_d), .wr_en_i (tmatch_control_we[i]), .rd_data_o (tmatch_control_q[i]), - .rd_error_o () + .rd_error_o (unused_error16) ); brq_csr #( @@ -1384,7 +1401,7 @@ .wr_data_i (tmatch_value_d), .wr_en_i (tmatch_value_we[i]), .rd_data_o (tmatch_value_q[i]), - .rd_error_o () + .rd_error_o (unused_error7) ); end
diff --git a/verilog/rtl/brq_idu.sv b/verilog/rtl/brq_idu.sv index df82b18..45c8c9c 100644 --- a/verilog/rtl/brq_idu.sv +++ b/verilog/rtl/brq_idu.sv
@@ -34,7 +34,7 @@ input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers input logic instr_is_compressed_i, - input logic instr_bp_taken_i, + // input logic instr_bp_taken_i, output logic instr_req_o, output logic instr_first_cycle_id_o, output logic instr_valid_clear_o, // kill instr in IF-ID reg @@ -48,7 +48,7 @@ output logic pc_set_o, output logic pc_set_spec_o, output brq_pkg::pc_sel_e pc_mux_o, - output logic nt_branch_mispredict_o, + //output logic nt_branch_mispredict_o, output brq_pkg::exc_pc_sel_e exc_pc_mux_o, output brq_pkg::exc_cause_e exc_cause_o, @@ -599,7 +599,7 @@ .instr_i ( instr_rdata_i ), .instr_compressed_i ( instr_rdata_c_i ), .instr_is_compressed_i ( instr_is_compressed_i ), - .instr_bp_taken_i ( instr_bp_taken_i ), + // .instr_bp_taken_i ( instr_bp_taken_i ), .instr_fetch_err_i ( instr_fetch_err_i ), .instr_fetch_err_plus2_i ( instr_fetch_err_plus2_i ), .pc_id_i ( pc_id_i ), @@ -614,7 +614,7 @@ .pc_set_o ( pc_set_o ), .pc_set_spec_o ( pc_set_spec_o ), .pc_mux_o ( pc_mux_o ), - .nt_branch_mispredict_o ( nt_branch_mispredict_o ), + // .nt_branch_mispredict_o ( nt_branch_mispredict_o ), .exc_pc_mux_o ( exc_pc_mux_o ), .exc_cause_o ( exc_cause_o ), @@ -627,7 +627,7 @@ // jump/branch control .branch_set_i ( branch_set ), .branch_set_spec_i ( branch_set_spec ), - .branch_not_set_i ( branch_not_set ), + //.branch_not_set_i ( branch_not_set ), .jump_set_i ( jump_set ), // interrupt signals
diff --git a/verilog/rtl/brq_idu_controller.sv b/verilog/rtl/brq_idu_controller.sv index c35f470..1a66fbb 100644 --- a/verilog/rtl/brq_idu_controller.sv +++ b/verilog/rtl/brq_idu_controller.sv
@@ -25,7 +25,7 @@ input logic [31:0] instr_i, // uncompressed instr data for mtval input logic [15:0] instr_compressed_i, // instr compressed data for mtval input logic instr_is_compressed_i, // instr is compressed - input logic instr_bp_taken_i, // instr was predicted taken branch + // input logic instr_bp_taken_i, // instr was predicted taken branch input logic instr_fetch_err_i, // instr has error input logic instr_fetch_err_plus2_i, // instr error is x32 input logic [31:0] pc_id_i, // instr address @@ -42,7 +42,7 @@ output logic pc_set_spec_o, // speculative branch output brq_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector // (boot, normal, exception...) - output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was + // output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was // mispredicted (predicted taken) output brq_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC output brq_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs @@ -58,7 +58,7 @@ // taken) input logic branch_set_spec_i, // speculative branch signal (branch // may be taken) - input logic branch_not_set_i, // branch is definitely not taken + // input logic branch_not_set_i, // branch is definitely not taken input logic jump_set_i, // jump taken set signal // interrupt signals @@ -78,7 +78,7 @@ input logic debug_ebreakm_i, input logic debug_ebreaku_i, input logic trigger_match_i, - +// input logic instr_bp_taken_i, output logic csr_save_if_o, output logic csr_save_id_o, output logic csr_save_wb_o, @@ -103,7 +103,8 @@ input logic fpu_busy_i ); import brq_pkg::*; - + logic instr_bp_taken_i; + assign instr_bp_taken_i = '0; // FSM state encoding typedef enum logic [3:0] { RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH, @@ -357,7 +358,7 @@ pc_mux_o = PC_BOOT; pc_set_o = 1'b0; pc_set_spec_o = 1'b0; - nt_branch_mispredict_o = 1'b0; + //nt_branch_mispredict_o = 1'b0; exc_pc_mux_o = EXC_PC_IRQ; exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00 @@ -491,20 +492,20 @@ perf_jump_o = jump_set_i; end - if (BranchPredictor) begin - if (instr_bp_taken_i & branch_not_set_i) begin - // If the instruction is a branch that was predicted to be taken but was not taken - // signal a mispredict. - nt_branch_mispredict_o = 1'b1; - end - end + // if (BranchPredictor) begin + // if (instr_bp_taken_i & branch_not_set_i) begin + // // If the instruction is a branch that was predicted to be taken but was not taken + // // signal a mispredict. + // nt_branch_mispredict_o = 1'b1; + // end + // end end // pc_set signal excluding branch taken condition if ((branch_set_spec_i || jump_set_i) && !special_req_branch) begin // Only speculatively set the PC if the branch predictor hasn't already done the branch // for us - pc_set_spec_o = BranchPredictor ? ~instr_bp_taken_i : 1'b1; + pc_set_spec_o = /*BranchPredictor ? ~instr_bp_taken_i : */1'b1; end // If entering debug mode or handling an IRQ the core needs to wait @@ -560,7 +561,7 @@ exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M; end else if (irqs_i.irq_software) begin exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M; - end else begin // irqs_i.irq_timer + end else if (irqs_i.irq_timer)begin // irqs_i.irq_timer exc_cause_o = EXC_CAUSE_IRQ_TIMER_M; end end
diff --git a/verilog/rtl/brq_idu_decoder.sv b/verilog/rtl/brq_idu_decoder.sv index 3b4c452..1e7c136 100644 --- a/verilog/rtl/brq_idu_decoder.sv +++ b/verilog/rtl/brq_idu_decoder.sv
@@ -96,8 +96,7 @@ // Floating point extensions IO output fpnew_pkg::roundmode_e fp_rounding_mode_o, // defines the rounding mode - output brq_pkg::op_b_sel_e fp_alu_op_b_mux_sel_o, // operand b selection: reg value or - // immediate + output logic [4:0] fp_rf_raddr_a_o, output logic [4:0] fp_rf_raddr_b_o, output logic [4:0] fp_rf_raddr_c_o, @@ -1001,7 +1000,6 @@ fp_alu_op_mod_o = 1'b0; fp_alu_operator_o = FMADD; - fp_alu_op_b_mux_sel_o = OP_B_IMM; // op_b_sel_e, OP_B_REG_B unique case (opcode_alu)
diff --git a/verilog/rtl/brq_ifu.sv b/verilog/rtl/brq_ifu.sv index 4331423..d44024c 100644 --- a/verilog/rtl/brq_ifu.sv +++ b/verilog/rtl/brq_ifu.sv
@@ -44,13 +44,13 @@ // instr_is_compressed_id_o = 1'b1 output logic instr_is_compressed_id_o, // compressed decoder thinks this // is a compressed instr - output logic instr_bp_taken_o, // instruction was predicted to be + // output logic instr_bp_taken_o, // instruction was predicted to be // a taken branch output logic instr_fetch_err_o, // bus error on fetch output logic instr_fetch_err_plus2_o, // bus error misaligned output logic illegal_c_insn_id_o, // compressed decoder thinks this // is an invalid instr - output logic dummy_instr_id_o, // Instruction is a dummy + // output logic dummy_instr_id_o, // Instruction is a dummy output logic [31:0] pc_if_o, output logic [31:0] pc_id_o, @@ -59,17 +59,9 @@ input logic pc_set_i, // set the PC to a new value input logic pc_set_spec_i, input brq_pkg::pc_sel_e pc_mux_i, // selector for PC multiplexer - input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was + // input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was // mispredicted (predicted taken) input brq_pkg::exc_pc_sel_e exc_pc_mux_i, // selects ISR address - input brq_pkg::exc_cause_e exc_cause, // selects ISR address for - // vectorized interrupt lines - input logic dummy_instr_en_i, - input logic [2:0] dummy_instr_mask_i, - input logic dummy_instr_seed_en_i, - input logic [31:0] dummy_instr_seed_i, - input logic icache_enable_i, - input logic icache_inval_i, // jump and branch target input logic [31:0] branch_target_ex_i, // branch/jump target address @@ -101,7 +93,6 @@ logic branch_spec; logic predicted_branch; logic [31:0] fetch_addr_n; - logic unused_fetch_addr_n0; logic fetch_valid; logic fetch_ready; @@ -117,13 +108,9 @@ logic [31:0] exc_pc; - logic [5:0] irq_id; - logic unused_irq_bit; logic if_id_pipe_reg_we; // IF-ID pipeline reg write enable - // Dummy instruction signals - logic stall_dummy_instr; logic [31:0] instr_out; logic instr_is_compressed_out; logic illegal_c_instr_out; @@ -134,16 +121,6 @@ brq_pkg::pc_sel_e pc_mux_internal; - logic [7:0] unused_boot_addr; - logic [7:0] unused_csr_mtvec; - - assign unused_boot_addr = boot_addr_i[7:0]; - assign unused_csr_mtvec = csr_mtvec_i[7:0]; - - // extract interrupt ID from exception cause - assign irq_id = {exc_cause}; - assign unused_irq_bit = irq_id[5]; // MSB distinguishes interrupts from exceptions - // exception PC selection mux always_comb begin : exc_pc_mux unique case (exc_pc_mux_i) @@ -177,83 +154,40 @@ // tell CS register file to initialize mtvec on boot assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i; - - if (ICache) begin : gen_ifu_icache - // Full I-Cache option - brq_ifu_icache #( - .BranchPredictor (BranchPredictor), - .ICacheECC (ICacheECC) - ) icache_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - - .req_i ( req_i ), - - .branch_i ( branch_req ), - .branch_spec_i ( branch_spec ), - .predicted_branch_i ( predicted_branch ), - .branch_mispredict_i ( nt_branch_mispredict_i ), - .addr_i ( {fetch_addr_n[31:1], 1'b0} ), - - .ready_i ( fetch_ready ), - .valid_o ( fetch_valid ), - .rdata_o ( fetch_rdata ), - .addr_o ( fetch_addr ), - .err_o ( fetch_err ), - .err_plus2_o ( fetch_err_plus2 ), - - .instr_req_o ( instr_req_o ), - .instr_addr_o ( instr_addr_o ), - .instr_gnt_i ( instr_gnt_i ), - .instr_rvalid_i ( instr_rvalid_i ), - .instr_rdata_i ( instr_rdata_i ), - .instr_err_i ( instr_err_i ), - .instr_pmp_err_i ( instr_pmp_err_i ), - - .icache_enable_i ( icache_enable_i ), - .icache_inval_i ( icache_inval_i ), - .busy_o ( prefetch_busy ) - ); - end else begin : gen_ifu_prefetch_buffer + // prefetch buffer, caches a fixed number of instructions - brq_ifu_prefetch_buffer #( - .BranchPredictor (BranchPredictor) - ) ifu_prefetch_buffer_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), + brq_ifu_prefetch_buffer #( + .BranchPredictor (BranchPredictor) + ) ifu_prefetch_buffer_i ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), - .req_i ( req_i ), + .req_i ( req_i ), - .branch_i ( branch_req ), - .branch_spec_i ( branch_spec ), - .predicted_branch_i ( predicted_branch ), - .branch_mispredict_i ( nt_branch_mispredict_i ), - .addr_i ( {fetch_addr_n[31:1], 1'b0} ), + .branch_i ( branch_req ), + .branch_spec_i ( branch_spec ), + .predicted_branch_i ( predicted_branch ), + // .branch_mispredict_i ( nt_branch_mispredict_i ), + .addr_i ( {fetch_addr_n[31:1], 1'b0} ), - .ready_i ( fetch_ready ), - .valid_o ( fetch_valid ), - .rdata_o ( fetch_rdata ), - .addr_o ( fetch_addr ), - .err_o ( fetch_err ), - .err_plus2_o ( fetch_err_plus2 ), + .ready_i ( fetch_ready ), + .valid_o ( fetch_valid ), + .rdata_o ( fetch_rdata ), + .addr_o ( fetch_addr ), + .err_o ( fetch_err ), + .err_plus2_o ( fetch_err_plus2 ), - .instr_req_o ( instr_req_o ), - .instr_addr_o ( instr_addr_o ), - .instr_gnt_i ( instr_gnt_i ), - .instr_rvalid_i ( instr_rvalid_i ), - .instr_rdata_i ( instr_rdata_i ), - .instr_err_i ( instr_err_i ), - .instr_pmp_err_i ( instr_pmp_err_i ), + .instr_req_o ( instr_req_o ), + .instr_addr_o ( instr_addr_o ), + .instr_gnt_i ( instr_gnt_i ), + .instr_rvalid_i ( instr_rvalid_i ), + .instr_rdata_i ( instr_rdata_i ), + .instr_err_i ( instr_err_i ), + .instr_pmp_err_i ( instr_pmp_err_i ), - .busy_o ( prefetch_busy ) - ); - // ICache tieoffs - logic unused_icen, unused_icinv; - assign unused_icen = icache_enable_i; - assign unused_icinv = icache_inval_i; - end - - assign unused_fetch_addr_n0 = fetch_addr_n[0]; + .busy_o ( prefetch_busy ) + ); + assign branch_req = pc_set_i | predict_branch_taken; assign branch_spec = pc_set_spec_i | predict_branch_taken; @@ -271,70 +205,16 @@ logic instr_is_compressed; brq_ifu_compressed_decoder ifu_compressed_decoder_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .valid_i ( fetch_valid & ~fetch_err ), .instr_i ( if_instr_rdata ), .instr_o ( instr_decompressed ), .is_compressed_o ( instr_is_compressed ), .illegal_instr_o ( illegal_c_insn ) ); - // Dummy instruction insertion - if (DummyInstructions) begin : gen_dummy_instr - logic insert_dummy_instr; - logic [31:0] dummy_instr_data; - - brq_ifu_dummy_instr dummy_instr_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .dummy_instr_en_i ( dummy_instr_en_i ), - .dummy_instr_mask_i ( dummy_instr_mask_i ), - .dummy_instr_seed_en_i ( dummy_instr_seed_en_i ), - .dummy_instr_seed_i ( dummy_instr_seed_i ), - .fetch_valid_i ( fetch_valid ), - .id_in_ready_i ( id_in_ready_i ), - .insert_dummy_instr_o ( insert_dummy_instr ), - .dummy_instr_data_o ( dummy_instr_data ) - ); - - // Mux between actual instructions and dummy instructions - assign instr_out = insert_dummy_instr ? dummy_instr_data : instr_decompressed; - assign instr_is_compressed_out = insert_dummy_instr ? 1'b0 : instr_is_compressed; - assign illegal_c_instr_out = insert_dummy_instr ? 1'b0 : illegal_c_insn; - assign instr_err_out = insert_dummy_instr ? 1'b0 : if_instr_err; - - // Stall the IF stage if we insert a dummy instruction. The dummy will execute between whatever - // is currently in the ID stage and whatever is valid from the prefetch buffer this cycle. The - // PC of the dummy instruction will match whatever is next from the prefetch buffer. - assign stall_dummy_instr = insert_dummy_instr; - - // Register the dummy instruction indication into the ID stage - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - dummy_instr_id_o <= 1'b0; - end else if (if_id_pipe_reg_we) begin - dummy_instr_id_o <= insert_dummy_instr; - end - end - - end else begin : gen_no_dummy_instr - logic unused_dummy_en; - logic [2:0] unused_dummy_mask; - logic unused_dummy_seed_en; - logic [31:0] unused_dummy_seed; - - assign unused_dummy_en = dummy_instr_en_i; - assign unused_dummy_mask = dummy_instr_mask_i; - assign unused_dummy_seed_en = dummy_instr_seed_en_i; - assign unused_dummy_seed = dummy_instr_seed_i; - assign instr_out = instr_decompressed; - assign instr_is_compressed_out = instr_is_compressed; - assign illegal_c_instr_out = illegal_c_insn; - assign instr_err_out = if_instr_err; - assign stall_dummy_instr = 1'b0; - assign dummy_instr_id_o = 1'b0; - end + assign instr_out = instr_decompressed; + assign instr_is_compressed_out = instr_is_compressed; + assign illegal_c_instr_out = illegal_c_insn; + assign instr_err_out = if_instr_err; // The ID stage becomes valid as soon as any instruction is registered in the ID stage flops. // Note that the current instruction is squashed by the incoming pc_set_i signal. @@ -374,128 +254,20 @@ end end - // Check for expected increments of the PC when security hardening enabled - if (PCIncrCheck) begin : g_secure_pc - logic [31:0] prev_instr_addr_incr; - logic prev_instr_seq_q, prev_instr_seq_d; - - // Do not check for sequential increase after a branch, jump, exception, interrupt or debug - // request, all of which will set branch_req. Also do not check after reset or for dummys. - assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) & - ~branch_req & ~stall_dummy_instr; - - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - prev_instr_seq_q <= 1'b0; - end else begin - prev_instr_seq_q <= prev_instr_seq_d; - end - end - - assign prev_instr_addr_incr = pc_id_o + ((instr_is_compressed_id_o && !instr_fetch_err_o) ? - 32'd2 : 32'd4); - - // Check that the address equals the previous address +2/+4 - assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr); - - end else begin : g_no_secure_pc - assign pc_mismatch_alert_o = 1'b0; - end - - if (BranchPredictor) begin : g_ifu_branch_predictor - logic [31:0] instr_skid_data_q; - logic [31:0] instr_skid_addr_q; - logic instr_skid_bp_taken_q; - logic instr_skid_valid_q, instr_skid_valid_d; - logic instr_skid_en; - logic instr_bp_taken_q, instr_bp_taken_d; - - logic predict_branch_taken_raw; - - // ID stages needs to know if branch was predicted taken so it can signal mispredicts - always_ff @(posedge clk_i) begin - if (if_id_pipe_reg_we) begin - instr_bp_taken_q <= instr_bp_taken_d; - end - end - - // When branch prediction is enabled a skid buffer between the IF and ID/EX stage is introduced. - // If an instruction in IF is predicted to be a taken branch and ID/EX is not ready the - // instruction in IF is moved to the skid buffer which becomes the output of the IF stage until - // the ID/EX stage accepts the instruction. The skid buffer is required as otherwise the ID/EX - // ready signal is coupled to the instr_req_o output which produces a feedthrough path from - // data_gnt_i -> instr_req_o (which needs to be avoided as for some interconnects this will - // result in a combinational loop). - - assign instr_skid_en = predicted_branch & ~id_in_ready_i & ~instr_skid_valid_q; - - assign instr_skid_valid_d = (instr_skid_valid_q & ~id_in_ready_i & ~stall_dummy_instr) | - instr_skid_en; - - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - instr_skid_valid_q <= 1'b0; - end else begin - instr_skid_valid_q <= instr_skid_valid_d; - end - end - - always_ff @(posedge clk_i) begin - if (instr_skid_en) begin - instr_skid_bp_taken_q <= predict_branch_taken; - instr_skid_data_q <= fetch_rdata; - instr_skid_addr_q <= fetch_addr; - end - end - - brq_ifu_branch_predict branch_predict_i ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .fetch_rdata_i ( fetch_rdata ), - .fetch_pc_i ( fetch_addr ), - .fetch_valid_i ( fetch_valid ), - - .predict_branch_taken_o ( predict_branch_taken_raw ), - .predict_branch_pc_o ( predict_branch_pc ) - ); - - // If there is an instruction in the skid buffer there must be no branch prediction. - // Instructions are only placed in the skid after they have been predicted to be a taken branch - // so with the skid valid any prediction has already occurred. - // Do not branch predict on instruction errors. - assign predict_branch_taken = predict_branch_taken_raw & ~instr_skid_valid_q & ~fetch_err; - - // pc_set_i takes precendence over branch prediction - assign predicted_branch = predict_branch_taken & ~pc_set_i; - - assign if_instr_valid = fetch_valid | instr_skid_valid_q; - assign if_instr_rdata = instr_skid_valid_q ? instr_skid_data_q : fetch_rdata; - assign if_instr_addr = instr_skid_valid_q ? instr_skid_addr_q : fetch_addr; - - // Don't branch predict on instruction error so only instructions without errors end up in the - // skid buffer. - assign if_instr_err = ~instr_skid_valid_q & fetch_err; - assign instr_bp_taken_d = instr_skid_valid_q ? instr_skid_bp_taken_q : predict_branch_taken; - - assign fetch_ready = id_in_ready_i & ~stall_dummy_instr & ~instr_skid_valid_q; - - assign instr_bp_taken_o = instr_bp_taken_q; - - - end else begin : g_no_ifu_branch_predictor - assign instr_bp_taken_o = 1'b0; - assign predict_branch_taken = 1'b0; - assign predicted_branch = 1'b0; - assign predict_branch_pc = 32'b0; - - assign if_instr_valid = fetch_valid; - assign if_instr_rdata = fetch_rdata; - assign if_instr_addr = fetch_addr; - assign if_instr_err = fetch_err; - assign fetch_ready = id_in_ready_i & ~stall_dummy_instr; - end - + assign pc_mismatch_alert_o = 1'b0; + + // end else begin : g_no_ifu_branch_predictor + // assign instr_bp_taken_o = 1'b0; + assign predict_branch_taken = 1'b0; + assign predicted_branch = 1'b0; + assign predict_branch_pc = 32'b0; - + assign if_instr_valid = fetch_valid; + assign if_instr_rdata = fetch_rdata; + assign if_instr_addr = fetch_addr; + assign if_instr_err = fetch_err; + assign fetch_ready = id_in_ready_i; //& ~stall_dummy_instr; + // end + endmodule \ No newline at end of file
diff --git a/verilog/rtl/brq_ifu_compressed_decoder.sv b/verilog/rtl/brq_ifu_compressed_decoder.sv index 1a6fc57..b615e9a 100644 --- a/verilog/rtl/brq_ifu_compressed_decoder.sv +++ b/verilog/rtl/brq_ifu_compressed_decoder.sv
@@ -9,9 +9,6 @@ module brq_ifu_compressed_decoder ( - input logic clk_i, - input logic rst_ni, - input logic valid_i, input logic [31:0] instr_i, output logic [31:0] instr_o, output logic is_compressed_o, @@ -21,8 +18,6 @@ // valid_i indicates if instr_i is valid and is used for assertions only. // The following signal is used to avoid possible lint errors. - logic unused_valid; - assign unused_valid = valid_i; //////////////////////// // Compressed decoder //
diff --git a/verilog/rtl/brq_ifu_prefetch_buffer.sv b/verilog/rtl/brq_ifu_prefetch_buffer.sv index f366518..cfcc050 100644 --- a/verilog/rtl/brq_ifu_prefetch_buffer.sv +++ b/verilog/rtl/brq_ifu_prefetch_buffer.sv
@@ -16,7 +16,7 @@ input logic branch_i, input logic branch_spec_i, input logic predicted_branch_i, - input logic branch_mispredict_i, + // input logic branch_mispredict_i, input logic [31:0] addr_i, @@ -41,6 +41,8 @@ output logic busy_o ); + logic branch_mispredict_i; + assign branch_mispredict_i = '0; localparam int unsigned NUM_REQS = 2; logic branch_suppress;
diff --git a/verilog/rtl/brq_register_file_ff.sv b/verilog/rtl/brq_register_file_ff.sv index 9aa643e..ce7dbbd 100644 --- a/verilog/rtl/brq_register_file_ff.sv +++ b/verilog/rtl/brq_register_file_ff.sv
@@ -15,7 +15,7 @@ input logic clk_i, input logic rst_ni, - input logic test_en_i, + // input logic test_en_i, input logic dummy_instr_id_i, //Read port R1 @@ -92,7 +92,7 @@ assign rdata_b_o = rf_reg[raddr_b_i]; // Signal not used in FF register file - logic unused_test_en; - assign unused_test_en = test_en_i; + // logic unused_test_en; + // assign unused_test_en = test_en_i; endmodule
diff --git a/verilog/rtl/brq_wbu.sv b/verilog/rtl/brq_wbu.sv index 95e801c..54fa901 100644 --- a/verilog/rtl/brq_wbu.sv +++ b/verilog/rtl/brq_wbu.sv
@@ -54,7 +54,7 @@ input logic [4:0] fp_rf_waddr_id_i, input logic fp_rf_wen_id_i, output logic [31:0] fp_rf_wdata_wb_o, - output logic fp_load_i + input logic fp_load_i ); import brq_pkg::*; @@ -82,10 +82,7 @@ logic wb_valid_d; - // floating point - //logic [31:0] fp_rf_wdata_wb_q; logic fp_rf_we_wb_q; - //logic [4:0] fp_rf_waddr_wb_q; logic fp_load_q; // Stage becomes valid if an instruction enters for ID/EX and valid is cleared when instruction @@ -117,8 +114,6 @@ // added for floating point registers for wb stage fp_rf_we_wb_q <= fp_rf_wen_id_i; - // fp_rf_waddr_wb_q <= rf_waddr_id_i; - //fp_rf_wdata_wb_q <= rf_wdata_id_i; fp_load_q <= fp_load_i; end end
diff --git a/verilog/rtl/debug_rom.sv b/verilog/rtl/debug_rom.sv index 528c62c..a0e0208 100644 --- a/verilog/rtl/debug_rom.sv +++ b/verilog/rtl/debug_rom.sv
@@ -22,8 +22,8 @@ ); localparam int unsigned RomSize = 19; - logic [RomSize-1:0][63:0] mem; - assign mem = { + + const logic [RomSize-1:0][63:0] mem = { 64'h00000000_7b200073, 64'h7b202473_7b302573, 64'h10852423_f1402473,
diff --git a/verilog/rtl/debug_rom_one_scratch.sv b/verilog/rtl/debug_rom_one_scratch.sv index 3e88406..78d47be 100644 --- a/verilog/rtl/debug_rom_one_scratch.sv +++ b/verilog/rtl/debug_rom_one_scratch.sv
@@ -22,9 +22,8 @@ ); localparam int unsigned RomSize = 13; - logic [RomSize-1:0][63:0] mem; - assign mem = { + const logic [RomSize-1:0][63:0] mem = { 64'h00000000_7b200073, 64'h7b202473_10802423, 64'hf1402473_ab1ff06f,
diff --git a/verilog/rtl/fpnew_cast_multi.sv b/verilog/rtl/fpnew_cast_multi.sv index 98ed07b..f275553 100644 --- a/verilog/rtl/fpnew_cast_multi.sv +++ b/verilog/rtl/fpnew_cast_multi.sv
@@ -11,6 +11,7 @@ // Author: Stefan Mach <smach@iis.ee.ethz.ch> +`include "registers.svh" module fpnew_cast_multi #( parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1,
diff --git a/verilog/rtl/fpnew_divsqrt_multi.sv b/verilog/rtl/fpnew_divsqrt_multi.sv index 937d345..ac541a3 100644 --- a/verilog/rtl/fpnew_divsqrt_multi.sv +++ b/verilog/rtl/fpnew_divsqrt_multi.sv
@@ -11,7 +11,7 @@ // Author: Stefan Mach <smach@iis.ee.ethz.ch> - +`include "registers.svh" module fpnew_divsqrt_multi #( parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, // FPU configuration
diff --git a/verilog/rtl/fpnew_fma.sv b/verilog/rtl/fpnew_fma.sv index 420e793..552b98a 100644 --- a/verilog/rtl/fpnew_fma.sv +++ b/verilog/rtl/fpnew_fma.sv
@@ -11,6 +11,7 @@ // Author: Stefan Mach <smach@iis.ee.ethz.ch> +`include "registers.svh" module fpnew_fma #( parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), parameter int unsigned NumPipeRegs = 0, @@ -528,7 +529,7 @@ // or right of the (non-carry) MSB of the sum. always_comb begin : small_norm // Default assignment, discarding carry bit - {final_mantissa, sum_sticky_bits} = sum_shifted; + {final_mantissa[23:0], sum_sticky_bits} = sum_shifted; final_exponent = normalized_exponent; // The normalized sum has overflown, align right and fix exponent
diff --git a/verilog/rtl/fpnew_fma_multi.sv b/verilog/rtl/fpnew_fma_multi.sv index 840b889..9b7d7b9 100644 --- a/verilog/rtl/fpnew_fma_multi.sv +++ b/verilog/rtl/fpnew_fma_multi.sv
@@ -11,6 +11,7 @@ // Author: Stefan Mach <smach@iis.ee.ethz.ch> +`include "registers.svh" module fpnew_fma_multi #( parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, parameter int unsigned NumPipeRegs = 0,
diff --git a/verilog/rtl/fpnew_noncomp.sv b/verilog/rtl/fpnew_noncomp.sv index acddd48..0719c26 100644 --- a/verilog/rtl/fpnew_noncomp.sv +++ b/verilog/rtl/fpnew_noncomp.sv
@@ -11,7 +11,7 @@ // Author: Stefan Mach <smach@iis.ee.ethz.ch> - +`include "registers.svh" module fpnew_noncomp #( parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), parameter int unsigned NumPipeRegs = 0,
diff --git a/verilog/rtl/fpnew_opgroup_multifmt_slice.sv b/verilog/rtl/fpnew_opgroup_multifmt_slice.sv index 4f139e9..c4ee849 100644 --- a/verilog/rtl/fpnew_opgroup_multifmt_slice.sv +++ b/verilog/rtl/fpnew_opgroup_multifmt_slice.sv
@@ -11,6 +11,7 @@ // Author: Stefan Mach <smach@iis.ee.ethz.ch> +`include "registers.svh" module fpnew_opgroup_multifmt_slice #( parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::CONV, parameter int unsigned Width = 64,
diff --git a/verilog/rtl/pwm.v b/verilog/rtl/pwm.v new file mode 100644 index 0000000..017a89d --- /dev/null +++ b/verilog/rtl/pwm.v
@@ -0,0 +1,213 @@ +/* +control register [7:0]ctrl: +bit 0: When set, external clock is chosen for PWM/timer. When cleared, wb clock is used for PWM/timer. +bit 1: When set, PWM is enabled. When cleared, timer is enabled. +bit 2: When set, PWM/timer starts. When cleared, PWM/timer stops. +bit 3: When set, timer runs continuously. When cleared, timer runs one time. +bit 4: When set, o_pwm enabled. +bit 5: timer interrupt bit When it is written with 0, interrupt request is cleared. +bit 6: When set, a 16-bit external signal i_DC is used as duty cycle. When cleared, register DC is used. +bit 7: When set, counter reset for PWM/timer, it's output and bit 5 will also be cleared. When changing from PWM mode to timer mode reset is needed before timer starts. +*/ +module pwm( +//tlul interface + input clk_i, + input rst_ni, + + input re_i, + input we_i, + input [7:0] addr_i, + input [31:0] wdata_i, + input [3:0] be_i, + output [31:0] rdata_o, + output o_pwm, + output o_pwm_2, + output reg oe_pwm1, + output reg oe_pwm2 + +); + +////////////////////control logic//////////////////////////// +parameter adr_ctrl_1 = 0, + adr_divisor_1= 4, + adr_period_1 = 8, + adr_DC_1 = 12; + +parameter adr_ctrl_2 = 16, + adr_divisor_2= 20, + adr_period_2 = 24, + adr_DC_2 = 28; + + + + +reg [7:0] ctrl; +reg [15:0] period; +reg [15:0] DC_1; +reg [15:0] divisor; + +reg [7:0] ctrl_2; +reg [15:0] period_2; +reg [15:0] DC_2; +reg [15:0] divisor_2; + +wire write; + +assign write = we_i & ~re_i; + +always@(posedge clk_i) + if(~rst_ni)begin + ctrl[4:2] <= 0; + ctrl[0] <= 0; + ctrl[1] <= 1'b0; + ctrl[7:6] <= 0; + DC_1 <= 0; + period <= 0; + divisor <= 0; + + + ctrl_2[4:2] <= 0; + ctrl_2[0] <= 1'b0; + ctrl_2[7:6] <= 0; + ctrl_2[1] <= 1'b0; + DC_2 <= 0; + period_2 <= 0; + divisor_2 <= 0; + end + else if(write)begin + case(addr_i) + adr_ctrl_1:begin + ctrl[0] <= wdata_i[0]; + ctrl[1] <= 1'b1; + ctrl[4:2] <= wdata_i[4:2]; + ctrl[7:6] <= wdata_i[7:6]; + end + + adr_ctrl_2:begin + ctrl_2[0] <= wdata_i[0]; + ctrl_2[1] <= 1'b1; + ctrl_2[4:2] <= wdata_i[4:2]; + ctrl_2[7:6] <= wdata_i[7:6]; + end + + adr_divisor_1 : divisor <= wdata_i[15:0]; + adr_period_1 : period <= wdata_i[15:0]; + adr_DC_1 : DC_1 <= wdata_i[15:0]; + + adr_divisor_2 : divisor_2 <= wdata_i[15:0]; + adr_period_2 : period_2 <= wdata_i[15:0]; + adr_DC_2 : DC_2 <= wdata_i[15:0]; + endcase + end + +wire pwm_1; +assign pwm_1 = ctrl[1]; + +wire pwm_2; +assign pwm_2 = ctrl_2[1]; + +// clock division +reg clock_p1; +reg clock_p2; + +reg [15:0] counter_p1; +reg [15:0] counter_p2; +reg [15:0] period_counter1; +reg [15:0] period_counter2; + +reg pts; +reg pts_2; + +always @(posedge clk_i or negedge rst_ni) begin + if(~rst_ni) begin + clock_p1 <= 1'b0; + clock_p2 <= 1'b0; + counter_p1 <= 0; + counter_p2 <= 0; + end else begin + if(pwm_1) begin + counter_p1 <= counter_p1 + 1; + if(counter_p1 == divisor-1) begin + counter_p1 <= 0; + clock_p1 <= ~clock_p1; + end + end + + + if(pwm_2) begin + counter_p2 <= counter_p2 + 1; + if(counter_p2 == divisor_2-1) begin + counter_p2 <= 0; + clock_p2 <= ~clock_p2; + end + end + + end +end + + + + + +always@(posedge clock_p1 ) + if(~rst_ni)begin + pts <= 0; + period_counter1 <= 0; + end + else begin + if(ctrl[2])begin + if(pwm_1) begin + oe_pwm1 <= 1'b1; + if(period_counter1 >= period) period_counter1 <= 0; + else period_counter1 <= period_counter1+1; + + if(period_counter1 < DC_1) pts <= 1'b1; + else pts <= 1'b0; + end + end + else begin + pts <= 1'b0; + period_counter1 <= 0; + oe_pwm1 <= 0; + end +end + + + +always@(posedge clock_p2 ) + if(~rst_ni)begin + pts_2 <= 0; + period_counter2 <= 0; + end + else begin + if(ctrl_2[2])begin + if(pwm_2) begin + oe_pwm2 <= 1'b1; + if(period_counter2 >= period_2) period_counter2 <= 0; + else period_counter2 <= period_counter2+1; + + if(period_counter2 < DC_2) pts_2 <= 1'b1; + else pts_2 <= 1'b0; + end + end + else begin + pts_2 <= 1'b0; + period_counter2 <= 0; + oe_pwm2 <= 1'b0; + end +end +////////////////////////////////////////////////////////// + +assign o_pwm = ctrl[4]? pts: 0; +assign o_pwm_2 = ctrl_2[4]? pts_2: 0; +assign rdata_o = (addr_i == adr_ctrl_1) ? {8'h0,ctrl} : + (addr_i == adr_divisor_1)? divisor : + (addr_i == adr_period_1) ? period : + (addr_i == adr_DC_1) ? DC_1 : + (addr_i == adr_DC_2) ? DC_2 : + (addr_i == adr_period_2) ? period_2 : + (addr_i == adr_divisor_2)? divisor_2 : + (addr_i == adr_ctrl_2) ? {8'h0,ctrl_2}:0; + + +endmodule
diff --git a/verilog/rtl/pwm_top.sv b/verilog/rtl/pwm_top.sv index b159a93..5317159 100644 --- a/verilog/rtl/pwm_top.sv +++ b/verilog/rtl/pwm_top.sv
@@ -30,7 +30,7 @@ //assign err = '0; -PWM pwm_core( +pwm pwm_core( .clk_i (clk_i), .rst_ni (rst_ni), @@ -42,10 +42,6 @@ .be_i (be), .rdata_o (rdata), //.error_o (err), - -.i_extclk ('0), -.i_DC ('0), -.i_valid_DC ('0), .o_pwm (pwm_o), .o_pwm_2 (pwm_o_2), .oe_pwm1 (pwm1_oe),
diff --git a/verilog/rtl/registers.svh b/verilog/rtl/registers.svh new file mode 100644 index 0000000..c1975ed --- /dev/null +++ b/verilog/rtl/registers.svh
@@ -0,0 +1,224 @@ +// Copyright 2018 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Common register defines for RTL designs +`ifndef COMMON_CELLS_REGISTERS_SVH_ +`define COMMON_CELLS_REGISTERS_SVH_ + +// Abridged Summary of available FF macros: +// `FF: asynchronous active-low reset (implicit clock and reset) +// `FFAR: asynchronous active-high reset +// `FFARN: asynchronous active-low reset +// `FFSR: synchronous active-high reset +// `FFSRN: synchronous active-low reset +// `FFNR: without reset +// `FFL: load-enable and asynchronous active-low reset (implicit clock and reset) +// `FFLAR: load-enable and asynchronous active-high reset +// `FFLARN: load-enable and asynchronous active-low reset +// `FFLARNC: load-enable and asynchronous active-low reset and synchronous active-high clear +// `FFLSR: load-enable and synchronous active-high reset +// `FFLSRN: load-enable and synchronous active-low reset +// `FFLNR: load-enable without reset + + +// Flip-Flop with asynchronous active-low reset (implicit clock and reset) +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// Implicit: +// clk_i: clock input +// rst_ni: reset input (asynchronous, active low) +`define FF(__q, __d, __reset_value) \ + always_ff @(posedge clk_i or negedge rst_ni) begin \ + if (!rst_ni) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset +`define FFAR(__q, __d, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFARN(__q, __d, __reset_value, __clk, __arst_n) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input +`define FFSR(__q, __d, __reset_value, __clk, __reset_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : (__d); \ + end + +// Flip-Flop with synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input +`define FFSRN(__q, __d, __reset_value, __clk, __reset_n_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : (__d); \ + end + +// Always-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __clk: clock input +`define FFNR(__q, __d, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__d); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset (implicit clock and reset) +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// Implicit: +// clk_i: clock input +// rst_ni: reset input (asynchronous, active low) +`define FFL(__q, __d, __load, __reset_value) \ + always_ff @(posedge clk_i or negedge rst_ni) begin \ + if (!rst_ni) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset +`define FFLAR(__q, __d, __load, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFLARN(__q, __d, __load, __reset_value, __clk, __arst_n) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input +`define FFLSR(__q, __d, __load, __reset_value, __clk, __reset_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input +`define FFLSRN(__q, __d, __load, __reset_value, __clk, __reset_n_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset and synchronous clear +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clear: assign reset value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFLARNC(__q, __d, __load, __clear, __reset_value, __clk, __arst_n) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__clear`" *``/ \ + `endif \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__clear) ? (__reset_value) : (__load) ? (__d) : (__q); \ + end \ + end + +// Load-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clk: clock input +`define FFLNR(__q, __d, __load, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__load) ? (__d) : (__q); \ + end + +`endif
diff --git a/verilog/rtl/rv_plic.sv b/verilog/rtl/rv_plic.sv index 5d77a3b..fe41bf2 100644 --- a/verilog/rtl/rv_plic.sv +++ b/verilog/rtl/rv_plic.sv
@@ -65,21 +65,19 @@ assign cc_id = irq_id_o; always_comb begin + claim = '0; for (int i = 0 ; i < NumTarget ; i++) begin if (claim_re[i]) begin claim[claim_id[i]] = 1'b1; - end else begin - claim = '0; - end end end + end always_comb begin + complete = '0; for (int i = 0 ; i < NumTarget ; i++) begin if (complete_we[i]) begin complete[complete_id[i]] = 1'b1; - end else begin - complete = '0; - end + end end end
diff --git a/verilog/rtl/rv_plic_reg_pkg.sv b/verilog/rtl/rv_plic_reg_pkg.sv index ca7182f..cf016d7 100644 --- a/verilog/rtl/rv_plic_reg_pkg.sv +++ b/verilog/rtl/rv_plic_reg_pkg.sv
@@ -206,7 +206,7 @@ } rv_plic_reg2hw_threshold0_reg_t; typedef struct packed { - logic [7:0] q; + logic [5:0] q; logic qe; logic re; } rv_plic_reg2hw_cc0_reg_t; @@ -222,7 +222,7 @@ } rv_plic_hw2reg_ip_mreg_t; typedef struct packed { - logic [7:0] d; + logic [5:0] d; } rv_plic_hw2reg_cc0_reg_t;
diff --git a/verilog/rtl/rv_plic_reg_top.sv b/verilog/rtl/rv_plic_reg_top.sv index d7c1e35..61224c7 100644 --- a/verilog/rtl/rv_plic_reg_top.sv +++ b/verilog/rtl/rv_plic_reg_top.sv
@@ -513,8 +513,8 @@ logic [1:0] threshold0_qs; logic [1:0] threshold0_wd; logic threshold0_we; - logic [7:0] cc0_qs; - logic [7:0] cc0_wd; + logic [5:0] cc0_qs; + logic [5:0] cc0_wd; logic cc0_we; logic cc0_re; logic msip0_qs; @@ -5143,7 +5143,7 @@ // R[cc0]: V(True) prim_subreg_ext #( - .DW (8) + .DW (6) ) u_cc0 ( .re (cc0_re), .we (cc0_we),
diff --git a/verilog/rtl/spi_clgen.v b/verilog/rtl/spi_clgen.v index 2086eaa..e7eafcf 100644 --- a/verilog/rtl/spi_clgen.v +++ b/verilog/rtl/spi_clgen.v
@@ -1,4 +1,5 @@ - +// `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v" +`include "spi_defines.v" module spi_clgen ( input clk_i, // input clock (system clock)
diff --git a/verilog/rtl/spi_core.sv b/verilog/rtl/spi_core.sv index b1c2453..74d9df9 100644 --- a/verilog/rtl/spi_core.sv +++ b/verilog/rtl/spi_core.sv
@@ -1,4 +1,6 @@ - +// `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v" +//`include "/home/zeeshan/fyp/azadi/src/spi_host/rtl/spi_defines.v" +`include "spi_defines.v" module spi_core ( // tlul signals
diff --git a/verilog/rtl/spi_shift.v b/verilog/rtl/spi_shift.v index 9bc6067..efaf414 100644 --- a/verilog/rtl/spi_shift.v +++ b/verilog/rtl/spi_shift.v
@@ -1,4 +1,4 @@ - +`include "spi_defines.v" module spi_shift ( input clk_i, // system clock
diff --git a/verilog/rtl/spi_top.sv b/verilog/rtl/spi_top.sv index 6c65601..c99852f 100644 --- a/verilog/rtl/spi_top.sv +++ b/verilog/rtl/spi_top.sv
@@ -1,4 +1,6 @@ - +// `include "/home/merl/github_repos/azadi/src/spi_host/rtl/spi_defines.v" +//`include "/home/zeeshan/fyp/azadi/src/spi_host/rtl/spi_defines.v" +`include "spi_defines.v" module spi_top( input clk_i, @@ -72,4 +74,4 @@ .error_i (err) ); -endmodule +endmodule \ No newline at end of file
diff --git a/verilog/rtl/sram.v b/verilog/rtl/sram.v index 8fac671..bec8fd0 100644 --- a/verilog/rtl/sram.v +++ b/verilog/rtl/sram.v
@@ -9,6 +9,7 @@ parameter ADDR_WIDTH = 10 , parameter RAM_DEPTH = 1 << ADDR_WIDTH, // FIXME: This delay is arbitrary. + parameter DELAY = 3 , parameter VERBOSE = 1 , //Set to 0 to only display warnings parameter T_HOLD = 1 ,//Delay to hold dout value after posedge. Value is arbitrary parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over INITFILE) @@ -59,7 +60,7 @@ wmask0_reg = wmask0; addr0_reg = addr0; din0_reg = din0; - //dout0 = 32'bx; + //#(T_HOLD) dout0 = 32'bx; //if ( !csb0_reg && web0_reg && VERBOSE ) //$display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]); //if ( !csb0_reg && !web0_reg && VERBOSE )
diff --git a/verilog/rtl/sram_top.v b/verilog/rtl/sram_top.v new file mode 100644 index 0000000..d68b365 --- /dev/null +++ b/verilog/rtl/sram_top.v
@@ -0,0 +1,133 @@ +`include "utils.vh" +module sram_top + #( parameter NUM_WMASKS = 4, + parameter MEMD = 2048, + parameter DATA_WIDTH = 32, // data width + parameter nRPORTS = 1 , // number of reading ports + parameter nWPORTS = 1, // number of write ports + parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over IFILE) + parameter IFILE = "", // initialization mif file (don't pass extension), optional + parameter BASIC_MODEL = 1024, + parameter ADDR_WIDTH = 11, + parameter DELAY = 3 + )( /*`ifdef USE_POWER_PINS + inout vdd; + inout gnd; +`endif*/ + input clk, // clock + input csb, // active low chip select + input web, // active low write control + input [NUM_WMASKS-1:0] wmask, // write mask + input [ADDR_WIDTH-1:0] addr, + input [DATA_WIDTH-1:0] din, + output reg[DATA_WIDTH-1:0] dout, + input clk1, + input csb1, + input [ADDR_WIDTH-1:0] addr1, + output reg [DATA_WIDTH-1:0] dout1); + +localparam ADDRW = ADDR_WIDTH; // address width +localparam NUM_OF_BANKS = MEMD / BASIC_MODEL; +localparam Basic_ADDRW = `log2(BASIC_MODEL); // address width + +reg [DATA_WIDTH-1:0] RData_out; +wire[DATA_WIDTH-1:0] Rdata [NUM_OF_BANKS-1:0]; +wire [(NUM_OF_BANKS-1)/2:0] Addr_sel; +reg [(NUM_OF_BANKS-1)/2:0] Raddr_sel; +reg [Basic_ADDRW-1:0] Addr [NUM_OF_BANKS-1:0]; +reg wen [NUM_OF_BANKS-1:0]; +reg csb_i [NUM_OF_BANKS-1:0]; +reg web_reg; + +// port 2 +reg [DATA_WIDTH-1:0] RData_out_1; +wire[DATA_WIDTH-1:0] Rdata_1 [NUM_OF_BANKS-1:0]; +wire [(NUM_OF_BANKS-1)/2:0] Addr_sel_1; +reg [(NUM_OF_BANKS-1)/2:0] Raddr_sel_1; +reg [Basic_ADDRW-1:0] Addr_1 [NUM_OF_BANKS-1:0]; +reg csb_i_1 [NUM_OF_BANKS-1:0]; + + +assign Addr_sel = addr % NUM_OF_BANKS; +assign Addr_sel_1 = addr1 % NUM_OF_BANKS; + +always @(negedge clk) begin +Raddr_sel = addr % NUM_OF_BANKS; +Raddr_sel_1 = addr1 % NUM_OF_BANKS; +web_reg = web; +end + +integer i; +integer j; + + always @* begin + for(i=0; i<NUM_OF_BANKS; i=i+1) begin + Addr[i] = (Addr_sel == i) ? addr[ADDRW-1:ADDRW-Basic_ADDRW] : 0; + wen[i] = (Addr_sel == i) ? web : 1; + csb_i[i] = (Addr_sel == i) ? csb : 1; + end +end + +always @* begin + for(i=0; i<NUM_OF_BANKS; i=i+1) begin + Addr_1[i] = (Addr_sel_1 == i) ? addr1[ADDRW-1:ADDRW-Basic_ADDRW] : 0; + csb_i_1[i] = (Addr_sel_1 == i) ? csb1 : 1; + end +end + +genvar p; +generate + for(p=0; p<NUM_OF_BANKS; p=p+1) begin + sram #( .NUM_WMASKS (NUM_WMASKS), + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (Basic_ADDRW), + .RAM_DEPTH (BASIC_MODEL), + .DELAY(DELAY), + .IZERO(IZERO), + .IFILE(IFILE)) + sram_i( .clk0(clk), + .csb0(csb_i[p]), + .web0(wen[p]), + .wmask0(wmask), + .addr0(Addr[p]), + .din0(din), + .dout0(Rdata[p]), + .clk1(clk1), + .csb1(csb_i_1[p]), + .addr1(Addr_1[p]), + .dout1(Rdata_1[p])); + end +endgenerate + +always @(posedge clk) begin + if(web_reg==1) begin + for(j=0; j<NUM_OF_BANKS; j=j+1) begin + RData_out = (Raddr_sel == j) ? Rdata[j] : RData_out; + end + end + else + RData_out = RData_out; + // Port 2 +end +always @(posedge clk) begin + for(j=0; j<NUM_OF_BANKS; j=j+1) begin + //RData_out_1 = (Raddr_sel_1 == q) ? Rdata_1[q] : RData_out_1; + if(Raddr_sel_1 == j) + RData_out_1 = Rdata_1[j]; + else + RData_out_1 = RData_out_1; + end +end + + + +always @* begin +dout = RData_out; +end + +always @* begin +dout1 = RData_out_1; +end +endmodule + +
diff --git a/verilog/rtl/uart_rx_prog.v b/verilog/rtl/uart_rx_prog.v index fb43991..83c3e95 100644 --- a/verilog/rtl/uart_rx_prog.v +++ b/verilog/rtl/uart_rx_prog.v
@@ -1,4 +1,4 @@ - +`timescale 1ns / 1ps // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -153,4 +153,4 @@ assign o_Rx_DV = r_Rx_DV; assign o_Rx_Byte = r_Rx_Byte; -endmodule // uart_rx +endmodule // uart_rx \ No newline at end of file
diff --git a/verilog/rtl/utils.vh b/verilog/rtl/utils.vh new file mode 100644 index 0000000..6a8c518 --- /dev/null +++ b/verilog/rtl/utils.vh
@@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 2013, University of British Columbia (UBC); All rights reserved. // +// // +// Redistribution and use in source and binary forms, with or without // +// modification, are permitted provided that the following conditions are met: // +// * Redistributions of source code must retain the above copyright // +// notice, this list of conditions and the following disclaimer. // +// * Redistributions in binary form must reproduce the above copyright // +// notice, this list of conditions and the following disclaimer in the // +// documentation and/or other materials provided with the distribution. // +// * Neither the name of the University of British Columbia (UBC) nor the names // +// of its contributors may be used to endorse or promote products // +// derived from this software without specific prior written permission. // +// // +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE // +// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE // +// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL // +// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR // +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER // +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, // +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // +//////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////////// +// utils.vh: Design utilities (pre-compile) // +// // +// Author: Ameer M. Abdelhadi (ameer@ece.ubc.ca, ameer.abdelhadi@gmail.com) // +// SRAM-based Multi-ported RAMs; University of British Columbia (UBC), March 2013 // +//////////////////////////////////////////////////////////////////////////////////// + +`ifndef __UTILS_VH__ +`define __UTILS_VH__ + +`define DEBUG_MODE // debug mode, comment this line for other modes +`define VERBOSE // verbose debug, comment this line for other modes + +// Initiate Array structure - use once before calling packing/unpacking modules +`define ARRINIT integer _i_,_j_ +// pack/unpack 1D/2D/3D arrays; use in "always @*" if combinatorial +`define ARR2D1D(D1W,D2W, SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1) DST[((D2W)*_i_-1)-:D2W] = SRC[_i_-1] +`define ARR1D2D(D1W,D2W, SRC,DST) for(_i_=1;_i_<=(D1W);_i_=_i_+1) DST[_i_-1] = SRC[((D2W)*_i_-1)-:D2W] +`define ARR2D3D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][_j_-1] = SRC[_i_][((D3W)*_j_-1)-:D3W] +`define ARR3D2D(D1W,D2W,D3W,SRC,DST) for(_i_=0;_i_< (D1W);_i_=_i_+1) for(_j_=1;_j_<=(D2W);_j_=_j_+1) DST[_i_][((D3W)*_j_-1)-:D3W] = SRC[_i_][_j_-1] + +// print a 2-D array in a comma-delimited list +`define ARRPRN(ARRLEN,PRNSRC) for (_i_=(ARRLEN)-1;_i_>=0;_i_=_i_-1) $write("%c%h%c",(_i_==(ARRLEN)-1)?"[":"",PRNSRC[_i_],!_i_?"]":",") +// Initialize a vector with a specific width random number; extra bits are zero padded +`define GETRAND(RAND,RANDW) RAND=0; repeat ((RANDW)/32) RAND=(RAND<<32)|{$random}; RAND=(RAND<<((RANDW)%32))|({$random}>>(32-(RANDW)%32)) + +// factorial (n!) +`define fact(n) ( ( ((n) >= 2 ) ? 2 : 1) * \ + ( ((n) >= 3 ) ? 3 : 1) * \ + ( ((n) >= 4 ) ? 4 : 1) * \ + ( ((n) >= 5 ) ? 5 : 1) * \ + ( ((n) >= 6 ) ? 6 : 1) * \ + ( ((n) >= 7 ) ? 7 : 1) * \ + ( ((n) >= 8 ) ? 8 : 1) * \ + ( ((n) >= 9 ) ? 9 : 1) * \ + ( ((n) >= 10 ) ? 10 : 1) ) + +// ceiling of log2 +`define log2(x) ( ( ((x) > 1 ) ? 1 : 0) + \ + ( ((x) > 2 ) ? 1 : 0) + \ + ( ((x) > 4 ) ? 1 : 0) + \ + ( ((x) > 8 ) ? 1 : 0) + \ + ( ((x) > 16 ) ? 1 : 0) + \ + ( ((x) > 32 ) ? 1 : 0) + \ + ( ((x) > 64 ) ? 1 : 0) + \ + ( ((x) > 128 ) ? 1 : 0) + \ + ( ((x) > 256 ) ? 1 : 0) + \ + ( ((x) > 512 ) ? 1 : 0) + \ + ( ((x) > 1024 ) ? 1 : 0) + \ + ( ((x) > 2048 ) ? 1 : 0) + \ + ( ((x) > 4096 ) ? 1 : 0) + \ + ( ((x) > 8192 ) ? 1 : 0) + \ + ( ((x) > 16384 ) ? 1 : 0) + \ + ( ((x) > 32768 ) ? 1 : 0) + \ + ( ((x) > 65536 ) ? 1 : 0) + \ + ( ((x) > 131072 ) ? 1 : 0) + \ + ( ((x) > 262144 ) ? 1 : 0) + \ + ( ((x) > 524288 ) ? 1 : 0) + \ + ( ((x) > 1048576) ? 1 : 0) + \ + ( ((x) > 2097152) ? 1 : 0) + \ + ( ((x) > 4194304) ? 1 : 0) ) + +// floor of log2 +`define log2f(x) ( ( ((x) >= 2 ) ? 1 : 0) + \ + ( ((x) >= 4 ) ? 1 : 0) + \ + ( ((x) >= 8 ) ? 1 : 0) + \ + ( ((x) >= 16 ) ? 1 : 0) + \ + ( ((x) >= 32 ) ? 1 : 0) + \ + ( ((x) >= 64 ) ? 1 : 0) + \ + ( ((x) >= 128 ) ? 1 : 0) + \ + ( ((x) >= 256 ) ? 1 : 0) + \ + ( ((x) >= 512 ) ? 1 : 0) + \ + ( ((x) >= 1024 ) ? 1 : 0) + \ + ( ((x) >= 2048 ) ? 1 : 0) + \ + ( ((x) >= 4096 ) ? 1 : 0) + \ + ( ((x) >= 8192 ) ? 1 : 0) + \ + ( ((x) >= 16384 ) ? 1 : 0) + \ + ( ((x) >= 32768 ) ? 1 : 0) + \ + ( ((x) >= 65536 ) ? 1 : 0) + \ + ( ((x) >= 131072 ) ? 1 : 0) + \ + ( ((x) >= 262144 ) ? 1 : 0) + \ + ( ((x) >= 524288 ) ? 1 : 0) + \ + ( ((x) >= 1048576) ? 1 : 0) + \ + ( ((x) >= 2097152) ? 1 : 0) + \ + ( ((x) >= 4194304) ? 1 : 0) ) + +`endif //__UTILS_VH__