blob: 2fb91b3e44c1a41facd087ac327f3b2d9ccd9f60 [file] [log] [blame]
project:
category: Test Wafer
cover_image: docs/source/_static/user_proj_example.gds.png
description: At Libresilicon we have been working for several years on making chipdesign
and production available to a wider public. One big step is now to automatically
generate standard cell libraries just from the DRC rules and a given or even generated
netlist.
foundry: SkyWater
git_url: https://github.com/thesourcerer8/caravel_stdcelllib_stdcells_project.git
layout_image: ./gds/caravel.png
organization: Libresilicon Association
organization_url: http://libresilicon.com
owner: Philipp Guehring
process: SKY130
project_id: '00020011'
project_name: automaticstandardcelllibrary
shuttle_url: https://foss-eda-tools.googlesource.com/third_party/shuttle/mpw-two/slot-017.git
tags:
- Open MPW
- Test Wafer
- MPW2
- Libresilicon
- Librecell
- StdCellLib
top_level_netlist: caravel/verilog/gl/caravel.v
user_level_netlist: verilog/gl/user_project_wrapper.v
version: '1.00'