| commit | e0abf52eb8d66f029e1574fe582238ce9a2b9034 | [log] [tgz] |
|---|---|---|
| author | Mohamed Kassem <mkkassem@users.noreply.github.com> | Mon Apr 19 09:52:50 2021 -0700 |
| committer | GitHub <noreply@github.com> | Mon Apr 19 09:52:50 2021 -0700 |
| tree | e69c10c0e4a93364baab1efa5bd8a2873b223560 | |
| parent | 9cec2d3349f72f870af5e81f8e6032c92ee1bc10 [diff] |
Update README.md
diff --git a/README.md b/README.md index 9d7b656..4db9031 100644 --- a/README.md +++ b/README.md
@@ -70,7 +70,7 @@ Refer to [user_project_wrapper](verilog/rtl/user_project_wrapper.v) for more information. <p align=”center”> -<img src="docs/source_static/counter_32.png" width="50%" height="10%"> +<img src="docs/source/_static/counter_32.png" width="50%" height="10%"> </p> # Running Full Chip Simulation