Update full chip simulation to run from root
diff --git a/Makefile b/Makefile
index 43e7db2..16104a7 100644
--- a/Makefile
+++ b/Makefile
@@ -15,6 +15,7 @@
# SPDX-License-Identifier: Apache-2.0
CARAVEL_ROOT?=caravel
+SIM ?= RTL
# Install lite version of caravel, (1): caravel-lite, (0): caravel
CARAVEL_LITE?=1
@@ -39,10 +40,27 @@
.PHONY: verify
verify:
cd ./verilog/dv/ && \
- $(MAKE) -j$(THREADS) all
- cd ./verilog/dv/ && \
- SIM=GL $(MAKE) -j$(THREADS) all
+ export SIM=${SIM} && \
+ $(MAKE) -j$(THREADS)
+# Install DV setup
+.PHONY: simenv
+simenv:
+ docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+PDK_PATH=${PDK_ROOT}/sky130A
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% :
+ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_PATH}:${PDK_PATH} \
+ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+ -e TARGET_PATH=${TARGET_PATH} -e PDK_PATH=${PDK_PATH} \
+ -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+ -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+ sh -c $(VERIFY_COMMAND)
+
# Openlane Makefile Targets
BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
.PHONY: $(BLOCKS)
@@ -94,6 +112,11 @@
rm -rf $(CARAVEL_ROOT)
endif
+# Install Openlane
+.PHONY: openlane
+openlane:
+ cd openlane && $(MAKE) openlane
+
# Clean
.PHONY: clean
clean:
diff --git a/README.md b/README.md
index 3b7c1f9..4215dee 100644
--- a/README.md
+++ b/README.md
@@ -94,6 +94,24 @@
# Running Full Chip Simulation
+First, you will need to install the simulation environment, by
+
+```bash
+make simenv
+```
+
+This will pull a docker image with the needed tools installed.
+
+Then, run the RTL and GL simulation by
+
+```
+export CARAVEL_ROOT=$(pwd)/caravel
+# specify simulation model: RTL/GL
+export SIM=RTL
+# Run IO ports testbench, make verify-io_ports
+make verify-<dv-pattern>
+```
+
The verilog test-benches are under this directory [verilog/dv](verilog/dv). For more information on setting up the simulation environment and the available testbenches for this sample project, refer to [README](verilog/dv/README.md).
# Hardening the User Project Macro using Openlane
diff --git a/caravel b/caravel
index 02393a2..7a8e96c 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 02393a2ffd5676ce7c16fcba89e668f94d58f21f
+Subproject commit 7a8e96cfad2222d46e02c777a97761e70824813a
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 73d7868..d87238f 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -26,6 +26,10 @@
( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
done
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+$(DV_PATTERNS): verify-% :
+ cd $* && make
+
clean: ${PATTERNS}
for i in ${PATTERNS}; do \
( cd $$i && make clean ) ; \
diff --git a/verilog/dv/io_ports/Makefile b/verilog/dv/io_ports/Makefile
index c3a5e54..0ef079e 100644
--- a/verilog/dv/io_ports/Makefile
+++ b/verilog/dv/io_ports/Makefile
@@ -15,7 +15,7 @@
# SPDX-License-Identifier: Apache-2.0
## Caravel Pointers
-CARAVEL_ROOT ?= $(shell pwd)/../../../caravel-lite
+CARAVEL_ROOT ?= ../../../caravel
CARAVEL_PATH ?= $(CARAVEL_ROOT)
CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
index adae20d..b23075d 100644
--- a/verilog/dv/la_test1/Makefile
+++ b/verilog/dv/la_test1/Makefile
@@ -15,7 +15,7 @@
# SPDX-License-Identifier: Apache-2.0
## Caravel Pointers
-CARAVEL_ROOT ?= $(shell pwd)/../../../caravel-lite
+CARAVEL_ROOT ?= ../../../caravel
CARAVEL_PATH ?= $(CARAVEL_ROOT)
CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
index 6ba368f..14e48fc 100644
--- a/verilog/dv/la_test2/Makefile
+++ b/verilog/dv/la_test2/Makefile
@@ -15,7 +15,7 @@
# SPDX-License-Identifier: Apache-2.0
## Caravel Pointers
-CARAVEL_ROOT ?= $(shell pwd)/../../../caravel-lite
+CARAVEL_ROOT ?= ../../../caravel
CARAVEL_PATH ?= $(CARAVEL_ROOT)
CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index c9a6ca7..304d32c 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -15,7 +15,7 @@
# SPDX-License-Identifier: Apache-2.0
## Caravel Pointers
-CARAVEL_ROOT ?= $(shell pwd)/../../../caravel-lite
+CARAVEL_ROOT ?= ../../../caravel
CARAVEL_PATH ?= $(CARAVEL_ROOT)
CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 70ad01f..132a1cc 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -15,7 +15,7 @@
# SPDX-License-Identifier: Apache-2.0
## Caravel Pointers
-CARAVEL_ROOT ?= $(shell pwd)/../../../caravel-lite
+CARAVEL_ROOT ?= ../../../caravel
CARAVEL_PATH ?= $(CARAVEL_ROOT)
CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog
