clock frequency is made 50 MHz

verilog/rtl/user_proj_example.v

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 025636f..a32800c 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -87,7 +87,7 @@
     assign io_oeb[1] = 1'b0;
     assign RX_w = io_in[1];
     assign io_out[0] = TX_w;
-
+    assign io_oeb[(`MPRJ_IO_PADS-1):2] = {(`MPRJ_IO_PADS-3){rst}};
     // IRQ
     assign irq = 3'b000;	// Unused
 
@@ -96,8 +96,8 @@
     // Assuming LA probes [63:32] are for controlling the count register  
     assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
     // Assuming LA probes [65:64] are for controlling the count clk & reset  
-    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
-    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+    assign clk = wb_clk_i;
+    assign rst = wb_rst_i;
 /*
     counter #(
         .BITS(BITS)
@@ -152,7 +152,7 @@
     output    reg   TX=1            ,
     output    reg   bitti=0    
     );
-    reg [20:0]cycles_per_bit=868;
+    reg [20:0]cycles_per_bit=434;
     reg mesgul=1'b0;
     reg [3:0] index=4'b0;
     integer num_of_cycles=0;
@@ -249,7 +249,7 @@
     output  reg     corrupted
     );
  
-    reg[20:0] cycles_per_bit =868;
+    reg[20:0] cycles_per_bit =434;
     reg [3:0] index=4'd0;
     integer num_of_cycles=0;
     reg mesgul=0;