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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-002
/
slot-015
/
fa14e325ca198a100cfd2ac78190def0f51cd1ce
commit
fa14e325ca198a100cfd2ac78190def0f51cd1ce
[
log
]
author
manikandan-phd <manikandan_phd@outlook.com>
Sat Jun 19 04:30:10 2021 +0530
committer
manikandan-phd <manikandan_phd@outlook.com>
Sat Jun 19 04:30:10 2021 +0530
tree
ce7cc9ab838027d816dd189446d485c8080bbb75
parent
76ab1aa60324bb41a2a36a5586932f33c2bb4a5f
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diff
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final design for submission
verilog/gl/user_proj_example.v
[
diff
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1 file changed
tree: ce7cc9ab838027d816dd189446d485c8080bbb75
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
caravel
.gitignore
.gitmodules
info.yaml
LICENSE
Makefile
README.md
README.md
Caravel encoder
:exclamation: Important Note
Please fill in your project documentation in this README.md file
Refer to
README
for this sample project documentation.