Inserted submodule line

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..e9da81c 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,4 +25,5 @@
 `else
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
+    `include "Per_32B.v"
 `endif
\ No newline at end of file