commit e6de470f8b997b381eb1f79c9a4c12cdea68ad8f
author manikandan-phd <manikandan_phd@outlook.com> Fri Jun 18 02:37:59 2021 +0530
committer manikandan-phd <manikandan_phd@outlook.com> Fri Jun 18 02:37:59 2021 +0530
tree ff2c33ca533ca0930e99d76f8a9fc3f18a912919
parent 4a40b277da0aa17737139bd201033408ae9dd742

Inserted submodule line

verilog/rtl/uprj_netlists.v

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3537de8..e9da81c 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -25,4 +25,5 @@
 `else
     `include "user_project_wrapper.v"
     `include "user_proj_example.v"
+    `include "Per_32B.v"
 `endif
\ No newline at end of file