| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/user_proj_example,user_proj_example,user_proj_example,Flow_completed,1h39m16s,0h58m25s,8713.333333333334,1.2,4356.666666666667,4,820.12,5228,0,0,0,0,0,0,0,2,0,-1,-1,236299,66302,-47.36,-47.36,-38.22,-44.64,-39.73,-94.68,-94.68,-75.78,-75.78,-79.4,102903540,0.0,5.03,2.82,1.84,0.01,-1,5005,5595,34,624,0,0,0,5228,768,4,470,414,2216,2256,141,23,1473,1404,94,718,16241,13106,30065,16.742005692281936,59.73,20,AREA 0,5,50,1,153.6,153.18,0.5,0,sky130_fd_sc_hd,4,2 |
