final design for submission

diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 3a1ef84..28b2f47 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl

@@ -27,7 +27,7 @@
 set ::env(CLOCK_PERIOD) "20"
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1000 1000"
+set ::env(DIE_AREA) "0 0 1200 1000"
 set ::env(DESIGN_IS_CORE) 0
 
 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
@@ -40,5 +40,7 @@
 
 set ::env(DIODE_INSERTION_STRATEGY) "2"
 
+set ::env(GLB_RT_MAXLAYER) 5
+
 # If you're going to use multiple power domains, then keep this disabled.
 set ::env(RUN_CVC) 0