updated license info and added the description to the read me
diff --git a/verilog/rtl/ibex_int_controller.v b/verilog/rtl/ibex_int_controller.v
index 81dbf3f..515472c 100644
--- a/verilog/rtl/ibex_int_controller.v
+++ b/verilog/rtl/ibex_int_controller.v
@@ -1,3 +1,23 @@
+// Copyright lowRISC contributors.
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+////////////////////////////////////////////////////////////////////////////////
+// Engineer: Matthias Baer - baermatt@student.ethz.ch //
+// //
+// Additional contributions by: //
+// Sven Stucki - svstucki@student.ethz.ch //
+// //
+// //
+// Design Name: RISC-V processor core //
+// Project Name: ibex //
+// Language: SystemVerilog //
+// //
+// Description: Defines for various constants used by the processor core. //
+// //
+////////////////////////////////////////////////////////////////////////////////
+
module ibex_int_controller (
clk,
rst_n,
