update netlist
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index b513bb2..cfbcad3 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,41 +1,287 @@
-/* Generated by Yosys 0.9+4052 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) */
+module user_project_wrapper (user_clock2,
+ vccd1,
+ vccd2,
+ vdda1,
+ vdda2,
+ vssa1,
+ vssa2,
+ vssd1,
+ vssd2,
+ wb_clk_i,
+ wb_rst_i,
+ wbs_ack_o,
+ wbs_cyc_i,
+ wbs_stb_i,
+ wbs_we_i,
+ analog_io,
+ io_in,
+ io_oeb,
+ io_out,
+ la_data_in,
+ la_data_out,
+ la_oenb,
+ user_irq,
+ wbs_adr_i,
+ wbs_dat_i,
+ wbs_dat_o,
+ wbs_sel_i);
+ input user_clock2;
+ input vccd1;
+ input vccd2;
+ input vdda1;
+ input vdda2;
+ input vssa1;
+ input vssa2;
+ input vssd1;
+ input vssd2;
+ input wb_clk_i;
+ input wb_rst_i;
+ output wbs_ack_o;
+ input wbs_cyc_i;
+ input wbs_stb_i;
+ input wbs_we_i;
+ inout [28:0] analog_io;
+ input [37:0] io_in;
+ output [37:0] io_oeb;
+ output [37:0] io_out;
+ input [127:0] la_data_in;
+ output [127:0] la_data_out;
+ input [127:0] la_oenb;
+ output [2:0] user_irq;
+ input [31:0] wbs_adr_i;
+ input [31:0] wbs_dat_i;
+ output [31:0] wbs_dat_o;
+ input [3:0] wbs_sel_i;
-module user_project_wrapper(wb_clk_i, wb_rst_i, wbs_stb_i, wbs_cyc_i, wbs_we_i, wbs_sel_i, wbs_dat_i, wbs_adr_i, wbs_ack_o, wbs_dat_o, la_data_in, la_data_out, la_oenb, io_in, io_out, io_oeb, analog_io, user_clock2, user_irq);
- inout [28:0] analog_io;
- input [37:0] io_in;
- output [37:0] io_oeb;
- output [37:0] io_out;
- input [127:0] la_data_in;
- output [127:0] la_data_out;
- input [127:0] la_oenb;
- input user_clock2;
- output [2:0] user_irq;
- input wb_clk_i;
- input wb_rst_i;
- output wbs_ack_o;
- input [31:0] wbs_adr_i;
- input wbs_cyc_i;
- input [31:0] wbs_dat_i;
- output [31:0] wbs_dat_o;
- input [3:0] wbs_sel_i;
- input wbs_stb_i;
- input wbs_we_i;
- eFPGA_CPU_top inst_eFPGA_CPU_top (
- .io_in(io_in),
- .io_oeb(io_oeb),
- .io_out(io_out),
- .la_data_in(la_data_in[3:0]),
- .la_data_out(la_data_out[2:0]),
- .user_clock2(user_clock2),
- .wb_clk_i(wb_clk_i),
+
+ eFPGA_CPU_top inst_eFPGA_CPU_top (.wb_clk_i(wb_clk_i),
+ .vccd1(vccd1),
+ .vssd1(vssd1),
.wb_rst_i(wb_rst_i),
- .wbs_ack_o(wbs_ack_o),
- .wbs_adr_i(wbs_adr_i),
- .wbs_cyc_i(wbs_cyc_i),
- .wbs_dat_i(wbs_dat_i),
- .wbs_dat_o(wbs_dat_o),
- .wbs_sel_i(wbs_sel_i),
.wbs_stb_i(wbs_stb_i),
- .wbs_we_i(wbs_we_i)
- );
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_ack_o(wbs_ack_o),
+ .user_clock2(user_clock2),
+ .io_in({io_in[37],
+ io_in[36],
+ io_in[35],
+ io_in[34],
+ io_in[33],
+ io_in[32],
+ io_in[31],
+ io_in[30],
+ io_in[29],
+ io_in[28],
+ io_in[27],
+ io_in[26],
+ io_in[25],
+ io_in[24],
+ io_in[23],
+ io_in[22],
+ io_in[21],
+ io_in[20],
+ io_in[19],
+ io_in[18],
+ io_in[17],
+ io_in[16],
+ io_in[15],
+ io_in[14],
+ io_in[13],
+ io_in[12],
+ io_in[11],
+ io_in[10],
+ io_in[9],
+ io_in[8],
+ io_in[7],
+ io_in[6],
+ io_in[5],
+ io_in[4],
+ io_in[3],
+ io_in[2],
+ io_in[1],
+ io_in[0]}),
+ .io_oeb({io_oeb[37],
+ io_oeb[36],
+ io_oeb[35],
+ io_oeb[34],
+ io_oeb[33],
+ io_oeb[32],
+ io_oeb[31],
+ io_oeb[30],
+ io_oeb[29],
+ io_oeb[28],
+ io_oeb[27],
+ io_oeb[26],
+ io_oeb[25],
+ io_oeb[24],
+ io_oeb[23],
+ io_oeb[22],
+ io_oeb[21],
+ io_oeb[20],
+ io_oeb[19],
+ io_oeb[18],
+ io_oeb[17],
+ io_oeb[16],
+ io_oeb[15],
+ io_oeb[14],
+ io_oeb[13],
+ io_oeb[12],
+ io_oeb[11],
+ io_oeb[10],
+ io_oeb[9],
+ io_oeb[8],
+ io_oeb[7],
+ io_oeb[6],
+ io_oeb[5],
+ io_oeb[4],
+ io_oeb[3],
+ io_oeb[2],
+ io_oeb[1],
+ io_oeb[0]}),
+ .io_out({io_out[37],
+ io_out[36],
+ io_out[35],
+ io_out[34],
+ io_out[33],
+ io_out[32],
+ io_out[31],
+ io_out[30],
+ io_out[29],
+ io_out[28],
+ io_out[27],
+ io_out[26],
+ io_out[25],
+ io_out[24],
+ io_out[23],
+ io_out[22],
+ io_out[21],
+ io_out[20],
+ io_out[19],
+ io_out[18],
+ io_out[17],
+ io_out[16],
+ io_out[15],
+ io_out[14],
+ io_out[13],
+ io_out[12],
+ io_out[11],
+ io_out[10],
+ io_out[9],
+ io_out[8],
+ io_out[7],
+ io_out[6],
+ io_out[5],
+ io_out[4],
+ io_out[3],
+ io_out[2],
+ io_out[1],
+ io_out[0]}),
+ .la_data_in({la_data_in[3],
+ la_data_in[2],
+ la_data_in[1],
+ la_data_in[0]}),
+ .la_data_out({la_data_out[6],
+ la_data_out[5],
+ la_data_out[4]}),
+ .wbs_adr_i({wbs_adr_i[31],
+ wbs_adr_i[30],
+ wbs_adr_i[29],
+ wbs_adr_i[28],
+ wbs_adr_i[27],
+ wbs_adr_i[26],
+ wbs_adr_i[25],
+ wbs_adr_i[24],
+ wbs_adr_i[23],
+ wbs_adr_i[22],
+ wbs_adr_i[21],
+ wbs_adr_i[20],
+ wbs_adr_i[19],
+ wbs_adr_i[18],
+ wbs_adr_i[17],
+ wbs_adr_i[16],
+ wbs_adr_i[15],
+ wbs_adr_i[14],
+ wbs_adr_i[13],
+ wbs_adr_i[12],
+ wbs_adr_i[11],
+ wbs_adr_i[10],
+ wbs_adr_i[9],
+ wbs_adr_i[8],
+ wbs_adr_i[7],
+ wbs_adr_i[6],
+ wbs_adr_i[5],
+ wbs_adr_i[4],
+ wbs_adr_i[3],
+ wbs_adr_i[2],
+ wbs_adr_i[1],
+ wbs_adr_i[0]}),
+ .wbs_dat_i({wbs_dat_i[31],
+ wbs_dat_i[30],
+ wbs_dat_i[29],
+ wbs_dat_i[28],
+ wbs_dat_i[27],
+ wbs_dat_i[26],
+ wbs_dat_i[25],
+ wbs_dat_i[24],
+ wbs_dat_i[23],
+ wbs_dat_i[22],
+ wbs_dat_i[21],
+ wbs_dat_i[20],
+ wbs_dat_i[19],
+ wbs_dat_i[18],
+ wbs_dat_i[17],
+ wbs_dat_i[16],
+ wbs_dat_i[15],
+ wbs_dat_i[14],
+ wbs_dat_i[13],
+ wbs_dat_i[12],
+ wbs_dat_i[11],
+ wbs_dat_i[10],
+ wbs_dat_i[9],
+ wbs_dat_i[8],
+ wbs_dat_i[7],
+ wbs_dat_i[6],
+ wbs_dat_i[5],
+ wbs_dat_i[4],
+ wbs_dat_i[3],
+ wbs_dat_i[2],
+ wbs_dat_i[1],
+ wbs_dat_i[0]}),
+ .wbs_dat_o({wbs_dat_o[31],
+ wbs_dat_o[30],
+ wbs_dat_o[29],
+ wbs_dat_o[28],
+ wbs_dat_o[27],
+ wbs_dat_o[26],
+ wbs_dat_o[25],
+ wbs_dat_o[24],
+ wbs_dat_o[23],
+ wbs_dat_o[22],
+ wbs_dat_o[21],
+ wbs_dat_o[20],
+ wbs_dat_o[19],
+ wbs_dat_o[18],
+ wbs_dat_o[17],
+ wbs_dat_o[16],
+ wbs_dat_o[15],
+ wbs_dat_o[14],
+ wbs_dat_o[13],
+ wbs_dat_o[12],
+ wbs_dat_o[11],
+ wbs_dat_o[10],
+ wbs_dat_o[9],
+ wbs_dat_o[8],
+ wbs_dat_o[7],
+ wbs_dat_o[6],
+ wbs_dat_o[5],
+ wbs_dat_o[4],
+ wbs_dat_o[3],
+ wbs_dat_o[2],
+ wbs_dat_o[1],
+ wbs_dat_o[0]}),
+ .wbs_sel_i({wbs_sel_i[3],
+ wbs_sel_i[2],
+ wbs_sel_i[1],
+ wbs_sel_i[0]}));
endmodule
