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foss-eda-tools / third_party / shuttle / sky130 / mpw-002 / slot-010 / 9d1f9c8ff002a1abcd3e94f8aea653b8131b5b20
commit9d1f9c8ff002a1abcd3e94f8aea653b8131b5b20[log] [tgz]
authorabdullahyildiz <abdullah.yildiz@yongatek.com>Tue Jun 08 15:36:30 2021 +0300
committerabdullahyildiz <abdullah.yildiz@yongatek.com>Tue Jun 08 15:36:30 2021 +0300
tree64de61efddbdd90515d36eab8d96528d011b4a1d
parent953837e36773584117909f739f4b3820b12eabf8 [diff]
Create yonga_lz4_decoder_controller.v
1 file changed
tree: 64de61efddbdd90515d36eab8d96528d011b4a1d
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. caravel
  13. .gitignore
  14. .gitmodules
  15. info.yaml
  16. LICENSE
  17. Makefile
  18. README.md
README.md

YONGA-LZ4 Decoder

License UPRJ_CI Caravel Build

Table of contents

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

Simulation

TBA

Checklist for Open-MPW Submission

  • [] The project repo adheres to the same directory structure in this repo
  • [] The project repo contain info.yaml at the project root
  • [] Top level macro is named user_project_wrapper
  • [] Full Chip Simulation passes for RTL and GL (gate-level)
  • [] The hardened Macros are LVS and DRC clean
  • [] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
  • [] XOR check passes with zero total difference.
  • [] Openlane summary reports are retained under ./signoff/