commit: 5b5e1904570880e8edda0af9d0397739c2ea0df0
[log] [tgz]
author: abdullahyildiz <abdullah.yildiz@yongatek.com>
Tue Jun 08 15:36:43 2021 +0300
committer: abdullahyildiz <abdullah.yildiz@yongatek.com>
Tue Jun 08 15:36:43 2021 +0300
tree: 9ed4bca6c23cd11d7819de6cbe73707f6a299741
parent: 8e38c058d43caefeeebb1e2a1ad1c6d40e223556 [diff]

Create list_ch04_20_fifo.v

verilog/rtl/list_ch04_20_fifo.v[Added - diff]

1 file changed

tree: 9ed4bca6c23cd11d7819de6cbe73707f6a299741

README.md

YONGA-LZ4 Decoder

Table of contents

Overview
Simulation
Checklist for Open-MPW Submission

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

Simulation

TBA

Checklist for Open-MPW Submission

[] The project repo adheres to the same directory structure in this repo
[] The project repo contain info.yaml at the project root
[] Top level macro is named user_project_wrapper
[] Full Chip Simulation passes for RTL and GL (gate-level)
[] The hardened Macros are LVS and DRC clean
[] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
[] XOR check passes with zero total difference.
[] Openlane summary reports are retained under ./signoff/