commit 0fe2ac77b7d6a33f6f0cb7d4147f9a3c3ef0cf81
author abdullahyildiz <abdullah.yildiz@yongatek.com> Wed Jun 09 21:46:18 2021 +0300
committer abdullahyildiz <abdullah.yildiz@yongatek.com> Wed Jun 09 21:46:18 2021 +0300
tree f6b8a2c9b6deb8e546888b27f861d172a86532d6
parent a4450769bbe7144e26d5ca63254a468581562249

Update yonga_lz4_decoder.v

verilog/rtl/yonga_lz4_decoder.v

diff --git a/verilog/rtl/yonga_lz4_decoder.v b/verilog/rtl/yonga_lz4_decoder.v
index 4584f8b..fb92733 100644
--- a/verilog/rtl/yonga_lz4_decoder.v
+++ b/verilog/rtl/yonga_lz4_decoder.v
@@ -13,7 +13,7 @@
 // Last Changed Date : %%
 // Last Changed By   : 
 // Designer
-//          Name     : Bahadir TURKOGLU
+//          Name     : Bahadir TÜRKOGLU
 //          E-mail   : bahadir.turkoglu@yongatek.com          
 // =====================================================================================