commit: 0fe2ac77b7d6a33f6f0cb7d4147f9a3c3ef0cf81

[log]
author: abdullahyildiz <abdullah.yildiz@yongatek.com>

Wed Jun 09 21:46:18 2021 +0300
committer: abdullahyildiz <abdullah.yildiz@yongatek.com>

Wed Jun 09 21:46:18 2021 +0300
tree: f6b8a2c9b6deb8e546888b27f861d172a86532d6
parent: a4450769bbe7144e26d5ca63254a468581562249 [diff]

Update yonga_lz4_decoder.v

verilog/rtl/yonga_lz4_decoder.v[diff]

1 file changed

tree: f6b8a2c9b6deb8e546888b27f861d172a86532d6

README.md

YONGA-LZ4 Decoder

Table of contents

Overview
Simulation
Checklist for Open-MPW Submission

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

Simulation

TBA

Checklist for Open-MPW Submission

[] The project repo adheres to the same directory structure in this repo
[] The project repo contain info.yaml at the project root
[] Top level macro is named user_project_wrapper
[] Full Chip Simulation passes for RTL and GL (gate-level)
[] The hardened Macros are LVS and DRC clean
[] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
[] XOR check passes with zero total difference.
[] Openlane summary reports are retained under ./signoff/