Adding wrapper for control logic and SRAM modules

verilog/rtl/testchip/test_chip.v

diff --git a/verilog/rtl/testchip/test_chip.v b/verilog/rtl/testchip/test_chip.v
new file mode 100644
index 0000000..d332b8a
--- /dev/null
+++ b/verilog/rtl/testchip/test_chip.v
@@ -0,0 +1,10 @@
+`default_nettype  none

+

+

+module test_chip(

+    input clk_in,

+    input [55:0] analyzer_packet,

+    input [55:0] gpio_packet, 

+    output reg [31:0] sram_data

+);

+