Added global csr pin
diff --git a/verilog/dv/gpio_test/gpio_test.c b/verilog/dv/gpio_test/gpio_test.c
index 50ea61b..fa53b87 100644
--- a/verilog/dv/gpio_test/gpio_test.c
+++ b/verilog/dv/gpio_test/gpio_test.c
@@ -55,7 +55,7 @@
// Configure IO pin 21 as user output
// Observe value in the testbench
- reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
diff --git a/verilog/dv/gpio_test/gpio_test_tb.v b/verilog/dv/gpio_test/gpio_test_tb.v
index 131b5ff..c27fda7 100644
--- a/verilog/dv/gpio_test/gpio_test_tb.v
+++ b/verilog/dv/gpio_test/gpio_test_tb.v
@@ -30,9 +30,9 @@
wire gpio;
wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
+ wire mprj_io_22;
- assign mprj_io_0 = mprj_io[7:0];
+ assign mprj_io_0 = mprj_io[22];
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
@@ -42,7 +42,7 @@
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+ always #5 clock <= (clock === 1'b0);
initial begin
clock = 0;
@@ -51,7 +51,8 @@
initial begin
$dumpfile("gpio_test.vcd");
$dumpvars(0, gpio_test_tb);
-
+
+ /*
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
repeat (1000) @(posedge clock);
@@ -65,6 +66,7 @@
`endif
$display("%c[0m",27);
$finish;
+ */
end
initial begin
diff --git a/verilog/rtl/openram_testchip.v b/verilog/rtl/openram_testchip.v
index 50a227b..809d0b7 100644
--- a/verilog/rtl/openram_testchip.v
+++ b/verilog/rtl/openram_testchip.v
@@ -20,7 +20,7 @@
input gpio_in,
input gpio_scan,
input gpio_sram_load,
-
+ input global_csr,
// SRAM data outputs to be captured
input [`DATA_SIZE-1:0] sram0_data0,
input [`DATA_SIZE-1:0] sram0_data1,
@@ -131,13 +131,13 @@
left_addr0 = sram_register[`TOTAL_SIZE-`SELECT_SIZE-1:`TOTAL_SIZE-`SELECT_SIZE-`ADDR_SIZE];
left_din0 = sram_register[`DATA_SIZE+`PORT_SIZE+`WMASK_SIZE+1:`PORT_SIZE+`WMASK_SIZE+2];
- csb0_temp = gpio_scan | la_in_load | sram_register[`PORT_SIZE+`WMASK_SIZE+1];
+ csb0_temp = global_csr | sram_register[`PORT_SIZE+`WMASK_SIZE+1];
left_web0 = sram_register[`PORT_SIZE+`WMASK_SIZE];
left_wmask0 = sram_register[`PORT_SIZE+`WMASK_SIZE-1:`PORT_SIZE];
left_addr1 = sram_register[`PORT_SIZE-1:`DATA_SIZE+`WMASK_SIZE+2];
left_din1 = sram_register[`DATA_SIZE+`WMASK_SIZE+1:`WMASK_SIZE+2];
- csb1_temp = gpio_scan | la_in_load | sram_register[`WMASK_SIZE+1];
+ csb1_temp = global_csr | sram_register[`WMASK_SIZE+1];
left_web1 = sram_register[`WMASK_SIZE];
left_wmask1 = sram_register[`WMASK_SIZE-1:0];
end
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 2d92416..53569e8 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -98,17 +98,17 @@
wire gpio_sram_clk = io_in[18];
wire gpio_scan = io_in[19];
wire gpio_sram_load = io_in[20];
+ wire global_csr = io_in[21];
wire la_clk = la_data_in[127];
wire la_in_load = la_data_in[125];
wire la_sram_load = la_data_in[124];
-
- // Only io_out[21] is output
- assign io_oeb = ~(1'b1 << 21);
+ // Only io_out[22] is output
+ assign io_oeb = ~(1'b1 << 22);
// Assign other outputs to 0
- assign io_out[`MPRJ_IO_PADS-1:22] = 0;
+ assign io_out[`MPRJ_IO_PADS-1:23] = 0;
wire gpio_out;
- assign io_out[21] = gpio_out;
- assign io_out[20:0] = 0;
+ assign io_out[22] = gpio_out;
+ assign io_out[21:0] = 0;
// Selecting clock pin
reg clk;
@@ -119,6 +119,7 @@
openram_testchip CONTROL_LOGIC(
.resetn(resetn & wb_rst_i),
.clk(clk),
+ .global_csr(global_csr),
.gpio_scan(gpio_scan),
.gpio_sram_load(gpio_sram_load),
.la_in_load(la_in_load),
